We now output VHDL types in the correct order

[matthijs/master-project/cλash.git] / VHDLTypes.hs

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index c1d9332f993d340772e2d7d9cfbb19a60187ab52..61fb0035650002fa61c95db39bb6c56429114bfb 100644 (file)
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -51,6 +51,8 @@ type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
 data VHDLState = VHDLState {
   -- | A map of Core type -> VHDL Type
   vsTypes_      :: TypeMap,
+  -- | A list of type declarations
+  vsTypeDecls_  :: [AST.PackageDecItem],
   -- | A map of vector Core type -> VHDL type function
   vsTypeFuns_   :: TypeFunMap,
   -- | A map of HsFunction -> hardware signature (entity name, port names,