-- GHC API imports
import qualified Type
import qualified CoreSyn
+import qualified HscTypes
-- ForSyDe imports
import qualified ForSyDe.Backend.VHDL.AST as AST
data HType = StdType OrdType |
ADTType String [HType] |
VecType Int HType |
+ SizedWType Int |
+ RangedWType Int |
+ SizedIType Int |
BuiltinType String
deriving (Eq, Ord)
-- A map of a Haskell function to a hardware signature
type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
-data VHDLState = VHDLState {
+type TfpIntMap = Map.Map OrdType Int
+
+data TypeState = TypeState {
-- | A map of Core type -> VHDL Type
vsTypes_ :: TypeMap,
-- | A list of type declarations
vsTypeDecls_ :: [AST.PackageDecItem],
-- | A map of vector Core type -> VHDL type function
vsTypeFuns_ :: TypeFunMap,
+ vsTfpInts_ :: TfpIntMap,
+ vsHscEnv_ :: HscTypes.HscEnv
+}
+-- Derive accessors
+$( Data.Accessor.Template.deriveAccessors ''TypeState )
+-- Define a session
+type TypeSession = State.State TypeState
+
+data VHDLState = VHDLState {
+ -- | A subtype with typing info
+ vsType_ :: TypeState,
-- | A map of HsFunction -> hardware signature (entity name, port names,
-- etc.)
vsSignatures_ :: SignatureMap
-- | The state containing a VHDL Session
type VHDLSession = State.State VHDLState
--- | A substate containing just the types
-type TypeState = State.State TypeMap
-
-- A function that generates VHDL for a builtin function
type BuiltinBuilder =
(Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type