Put a TypeMark in a VHDLSignalmap.

[matthijs/master-project/cλash.git] / VHDLTypes.hs

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 34a2b503dc4df4c51ef523363f40caf1cb47ce5f..44696479e6719de98c5f3f67bdcd6aa261b7e808 100644 (file)
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -7,7 +7,7 @@ import qualified ForSyDe.Backend.VHDL.AST as AST
 
 import FlattenTypes
 
-type VHDLSignalMap = SignalMap AST.VHDLId
+type VHDLSignalMap = SignalMap (AST.VHDLId, AST.TypeMark)
 
 -- A description of a VHDL entity. Contains both the entity itself as well as
 -- info on how to map a haskell value (argument / result) on to the entity's