import FlattenTypes
import HsValueMap
+type VHDLSignalMapElement = (Maybe (AST.VHDLId, AST.TypeMark))
-- | A mapping from a haskell structure to the corresponding VHDL port
-- signature, or Nothing for values that do not translate to a port.
-type VHDLSignalMap = HsValueMap (Maybe (AST.VHDLId, AST.TypeMark))
+type VHDLSignalMap = HsValueMap VHDLSignalMapElement
-- A description of a VHDL entity. Contains both the entity itself as well as
-- info on how to map a haskell value (argument / result) on to the entity's
-- ports.
-data Entity = Entity {
+data Entity = Entity {
ent_id :: AST.VHDLId, -- The id of the entity
ent_args :: [VHDLSignalMap], -- A mapping of each function argument to port names
ent_res :: VHDLSignalMap -- A mapping of the function result to port names
} deriving (Show);
-- A orderable equivalent of CoreSyn's Type for use as a map key
-newtype OrdType = OrdType Type.Type
+newtype OrdType = OrdType { getType :: Type.Type }
instance Eq OrdType where
(OrdType a) == (OrdType b) = Type.tcEqType a b
instance Ord OrdType where
compare (OrdType a) (OrdType b) = Type.tcCmpType a b
--- A map of a Core type to the corresponding type name (and optionally, it's
--- declaration for non-primitive types).
+-- A map of a Core type to the corresponding type name
type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
-- A map of a Haskell function to a hardware signature
-- Derive accessors
$( Data.Accessor.Template.deriveAccessors ''VHDLSession )
+-- | The state containing a VHDL Session
type VHDLState = State.State VHDLSession
+-- | A substate containing just the types
+type TypeState = State.State TypeMap
+
-- vim: set ts=8 sw=2 sts=2 expandtab: