Don't generate ports for non-port signals.

[matthijs/master-project/cλash.git] / VHDLTypes.hs

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 44696479e6719de98c5f3f67bdcd6aa261b7e808..1704bb874dc453a4475fe1657eb622e638ccb02c 100644 (file)
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -7,12 +7,15 @@ import qualified ForSyDe.Backend.VHDL.AST as AST
 
 import FlattenTypes
 
-type VHDLSignalMap = SignalMap (AST.VHDLId, AST.TypeMark)
+-- | A mapping from a haskell structure to the corresponding VHDL port
+--   signature, or Nothing for values that do not translate to a port.
+type VHDLSignalMap = SignalMap (Maybe (AST.VHDLId, AST.TypeMark))
 
 -- A description of a VHDL entity. Contains both the entity itself as well as
 -- info on how to map a haskell value (argument / result) on to the entity's
 -- ports.
 data Entity = Entity {
+  ent_id     :: AST.VHDLId,           -- The id of the entity
   ent_args   :: [VHDLSignalMap],      -- A mapping of each function argument to port names
   ent_res    :: VHDLSignalMap,        -- A mapping of the function result to port names
   ent_decl   :: Maybe AST.EntityDec   -- The actual entity declaration. Can be empty for builtin functions.