Restructure a lot of VHDL generating code.

[matthijs/master-project/cλash.git] / VHDLTypes.hs

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 79d7675f68a48f3663782d0d6c6465d90c0ef871..3e2ebe09ffebc4c55493a34c8afe6792e9d19679 100644 (file)
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -78,10 +78,10 @@ type TypeState = State.State TypeMap
 
 -- A function that generates VHDL for a builtin function
 type BuiltinBuilder = 
-  CoreSyn.CoreBndr -- ^ The destination value
+  (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type
   -> CoreSyn.CoreBndr -- ^ The function called
-  -> [CoreSyn.CoreExpr] -- ^ The value arguments passed (excluding type and
-                        --   dictionary arguments).
+  -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The value arguments passed (excluding type and
+                    --   dictionary arguments).
   -> VHDLSession [AST.ConcSm] -- ^ The resulting concurrent statements.
 
 -- A map of a builtin function to VHDL function builder