import qualified OccName
import qualified Var
import qualified Id
+import qualified IdInfo
import qualified TyCon
import qualified Type
import qualified DataCon
in
res
+
-- Turn a VHDLName into an AST expression
vhdlNameToVHDLExpr = AST.PrimName
let name = Name.getOccString (TyCon.tyConName tycon)
case name of
"TFVec" -> mk_vector_ty ty
- -- "SizedWord" -> do
- -- res <- mk_vector_ty (sized_word_len ty) ty
- -- return $ Just $ (Arrow.second Left) res
+ "SizedWord" -> mk_unsigned_ty ty
+ "SizedInt" -> mk_signed_ty ty
"RangedWord" -> mk_natural_ty 0 (ranged_word_bound ty)
-- Create a custom type from this tycon
otherwise -> mk_tycon_ty tycon args
let ty_def = AST.SubtypeIn naturalTM (Just range)
return (Right (ty_id, Right ty_def))
+mk_unsigned_ty ::
+ Type.Type -- ^ Haskell type of the unsigned integer
+ -> TypeSession (Either String (AST.TypeMark, Either AST.TypeDef AST.SubtypeIn))
+mk_unsigned_ty ty = do
+ let size = sized_word_len ty
+ let ty_id = mkVHDLExtId $ "unsigned_" ++ show (size - 1)
+ let range = AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (size - 1))]
+ let ty_def = AST.SubtypeIn unsignedTM (Just range)
+ return (Right (ty_id, Right ty_def))
+
+mk_signed_ty ::
+ Type.Type -- ^ Haskell type of the signed integer
+ -> TypeSession (Either String (AST.TypeMark, Either AST.TypeDef AST.SubtypeIn))
+mk_signed_ty ty = do
+ let size = sized_word_len ty
+ let ty_id = mkVHDLExtId $ "signed_" ++ show (size - 1)
+ let range = AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (size - 1))]
+ let ty_def = AST.SubtypeIn signedTM (Just range)
+ return (Right (ty_id, Right ty_def))
+
-- Finds the field labels for VHDL type generated for the given Core type,
-- which must result in a record type.
getFieldLabels :: Type.Type -> TypeSession [AST.VHDLId]
case elem_htype_either of
-- Could create element type
Right elem_htype -> do
- len <- vec_len ty
+ len <- tfp_to_int (tfvec_len_ty ty)
return $ Right $ VecType len elem_htype
-- Could not create element type
Left err -> return $ Left $
"VHDLTools.mkHType: Can not construct vectortype for elementtype: " ++ pprString el_ty ++ "\n"
++ err
+ "SizedWord" -> do
+ len <- tfp_to_int (sized_word_len_ty ty)
+ return $ Right $ SizedWType len
+ "SizedInt" -> do
+ len <- tfp_to_int (sized_word_len_ty ty)
+ return $ Right $ SizedIType len
+ "RangedWord" -> do
+ bound <- tfp_to_int (ranged_word_bound_ty ty)
+ return $ Right $ RangedWType bound
otherwise -> do
mkTyConHType tycon args
Nothing -> return $ Right $ StdType $ OrdType ty
Left _ -> False
Right _ -> True
-vec_len :: Type.Type -> TypeSession Int
-vec_len ty = do
- veclens <- getA vsTfpInts
- let len_ty = tfvec_len_ty ty
- let existing_len = Map.lookup (OrdType len_ty) veclens
+tfp_to_int :: Type.Type -> TypeSession Int
+tfp_to_int ty = do
+ lens <- getA vsTfpInts
+ let existing_len = Map.lookup (OrdType ty) lens
case existing_len of
Just len -> return len
Nothing -> do
- let new_len = tfvec_len ty
- modA vsTfpInts (Map.insert (OrdType len_ty) (new_len))
+ let new_len = eval_tfp_int ty
+ modA vsTfpInts (Map.insert (OrdType ty) (new_len))
return new_len
\ No newline at end of file