import qualified Data.Foldable as Foldable
import qualified Maybe
import qualified Control.Monad as Monad
+import qualified Control.Arrow as Arrow
+import qualified Data.Traversable as Traversable
+import qualified Data.Monoid as Monoid
import qualified Type
import qualified TysWiredIn
import TranslatorTypes
import Pretty
-getDesignFile :: VHDLState AST.DesignFile
-getDesignFile = do
+getDesignFiles :: VHDLState [AST.DesignFile]
+getDesignFiles = do
-- Extract the library units generated from all the functions in the
-- session.
funcs <- getFuncs
- let units = concat $ map getLibraryUnits funcs
+ let units = Maybe.mapMaybe getLibraryUnits funcs
let context = [
AST.Library $ mkVHDLId "IEEE",
AST.Use $ (AST.NSimple $ mkVHDLId "IEEE.std_logic_1164") AST.:.: AST.All]
- return $ AST.DesignFile
- context
- units
+ return $ map (AST.DesignFile context) units
-- | Create an entity for a given function
createEntity ::
Nothing -> do return ()
-- Create an entity for all other functions
Just flatfunc ->
-
let
sigs = flat_sigs flatfunc
args = flat_args flatfunc
res = flat_res flatfunc
- args' = map (fmap (mkMap sigs)) args
- res' = fmap (mkMap sigs) res
+ (ty_decls, args') = Traversable.traverse (Traversable.traverse (mkMap sigs)) args
+ (ty_decls', res') = Traversable.traverse (mkMap sigs) res
+ -- TODO: Unique ty_decls
ent_decl' = createEntityAST hsfunc args' res'
+ pkg_id = mkVHDLId $ (AST.fromVHDLId entity_id) ++ "_types"
+ pkg_decl = if null ty_decls && null ty_decls'
+ then Nothing
+ else Just $ AST.PackageDec pkg_id (map AST.PDITD $ ty_decls ++ ty_decls')
AST.EntityDec entity_id _ = ent_decl'
- entity' = Entity entity_id args' res' (Just ent_decl')
- in
+ entity' = Entity entity_id args' res' (Just ent_decl') pkg_decl
+ in do
setEntity hsfunc entity'
where
- mkMap :: Eq id => [(id, SignalInfo)] -> id -> Maybe (AST.VHDLId, AST.TypeMark)
+ mkMap ::
+ [(SignalId, SignalInfo)]
+ -> SignalId
+ -> ([AST.TypeDec], Maybe (AST.VHDLId, AST.TypeMark))
mkMap sigmap id =
if isPortSigUse $ sigUse info
then
- Just (mkVHDLId nm, vhdl_ty ty)
+ let (decs, type_mark) = vhdl_ty ty in
+ (decs, Just (mkVHDLId nm, type_mark))
else
- Nothing
+ (Monoid.mempty, Nothing)
where
info = Maybe.fromMaybe
(error $ "Signal not found in the name map? This should not happen!")
(getEntityId fdata)
-- Create signal declarations for all signals that are not in args and
-- res
- let sig_decs = Maybe.catMaybes $ map (mkSigDec . snd) sigs
+ let (ty_decls, sig_decs) = Arrow.second Maybe.catMaybes $ Traversable.traverse (mkSigDec . snd) sigs
+ -- TODO: Unique ty_decls
+ -- TODO: Store ty_decls somewhere
-- Create concurrent statements for all signal definitions
statements <- mapM (mkConcSm sigs) defs
- let procs = map mkStateProcSm (getOwnStates hsfunc flatfunc)
+ let procs = map mkStateProcSm (makeStatePairs flatfunc)
let procs' = map AST.CSPSm procs
let arch = AST.ArchBody (mkVHDLId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs')
setArchitecture hsfunc arch
+-- | Looks up all pairs of old state, new state signals, together with
+-- the state id they represent.
+makeStatePairs :: FlatFunction -> [(StateId, SignalInfo, SignalInfo)]
+makeStatePairs flatfunc =
+ [(Maybe.fromJust $ oldStateId $ sigUse old_info, old_info, new_info)
+ | old_info <- map snd (flat_sigs flatfunc)
+ , new_info <- map snd (flat_sigs flatfunc)
+ -- old_info must be an old state (and, because of the next equality,
+ -- new_info must be a new state).
+ , Maybe.isJust $ oldStateId $ sigUse old_info
+ -- And the state numbers must match
+ , (oldStateId $ sigUse old_info) == (newStateId $ sigUse new_info)]
+
+ -- Replace the second tuple element with the corresponding SignalInfo
+ --args_states = map (Arrow.second $ signalInfo sigs) args
mkStateProcSm :: (StateId, SignalInfo, SignalInfo) -> AST.ProcSm
mkStateProcSm (num, old, new) =
AST.ProcSm label [clk] [statement]
rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clk)]
statement = AST.IfSm rising_edge_clk [assign] [] Nothing
-mkSigDec :: SignalInfo -> Maybe AST.SigDec
+mkSigDec :: SignalInfo -> ([AST.TypeDec], Maybe AST.SigDec)
mkSigDec info =
let use = sigUse info in
if isInternalSigUse use || isStateSigUse use then
- Just $ AST.SigDec (getSignalId info) (vhdl_ty ty) Nothing
+ let (ty_decls, type_mark) = vhdl_ty ty in
+ (ty_decls, Just $ AST.SigDec (getSignalId info) type_mark Nothing)
else
- Nothing
+ ([], Nothing)
where
ty = sigTy info
(funcEntity fdata)
let entity_id = ent_id entity
label <- uniqueName (AST.fromVHDLId entity_id)
- let portmaps = mkAssocElems sigs args res entity
+ -- Add a clk port if we have state
+ let clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLId "clk") "clk"
+ let portmaps = mkAssocElems sigs args res entity ++ (if hasState hsfunc then [clk_port] else [])
return $ AST.CSISm $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
mkConcSm sigs (UncondDef src dst) = do
getLibraryUnits ::
(HsFunction, FuncData) -- | A function from the session
- -> [AST.LibraryUnit] -- | The library units it generates
+ -> Maybe [AST.LibraryUnit] -- | The entity, architecture and optional package for the function
getLibraryUnits (hsfunc, fdata) =
case funcEntity fdata of
- Nothing -> []
- Just ent -> case ent_decl ent of
- Nothing -> []
- Just decl -> [AST.LUEntity decl]
- ++
- case funcArch fdata of
- Nothing -> []
- Just arch -> [AST.LUArch arch]
+ Nothing -> Nothing
+ Just ent ->
+ case ent_decl ent of
+ Nothing -> Nothing
+ Just decl ->
+ case funcArch fdata of
+ Nothing -> Nothing
+ Just arch ->
+ Just $
+ [AST.LUEntity decl, AST.LUArch arch]
+ ++ (Maybe.maybeToList (fmap AST.LUPackageDec $ ent_pkg_decl ent))
-- | The VHDL Bit type
bit_ty :: AST.TypeMark
std_logic_ty = AST.unsafeVHDLBasicId "std_logic"
-- Translate a Haskell type to a VHDL type
-vhdl_ty :: Type.Type -> AST.TypeMark
+vhdl_ty :: Type.Type -> ([AST.TypeDec], AST.TypeMark)
vhdl_ty ty = Maybe.fromMaybe
(error $ "Unsupported Haskell type: " ++ (showSDoc $ ppr ty))
(vhdl_ty_maybe ty)
--- Translate a Haskell type to a VHDL type
-vhdl_ty_maybe :: Type.Type -> Maybe AST.TypeMark
+-- Translate a Haskell type to a VHDL type, optionally generating a type
+-- declaration for the type.
+vhdl_ty_maybe :: Type.Type -> Maybe ([AST.TypeDec], AST.TypeMark)
vhdl_ty_maybe ty =
if Type.coreEqType ty TysWiredIn.boolTy
then
- Just bool_ty
+ Just ([], bool_ty)
else
case Type.splitTyConApp_maybe ty of
Just (tycon, args) ->
let name = TyCon.tyConName tycon in
-- TODO: Do something more robust than string matching
case Name.getOccString name of
- "Bit" -> Just std_logic_ty
+ "Bit" -> Just ([], std_logic_ty)
+ "FSVec" ->
+ let
+ [len, el_ty] = args
+ -- TODO: Find actual number
+ ty_id = mkVHDLId ("vector_" ++ (show len))
+ -- TODO: Use el_ty
+ range = AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "16")]
+ ty_def = AST.TDA $ AST.ConsArrayDef range std_logic_ty
+ ty_dec = AST.TypeDec ty_id ty_def
+ in
+ Just ([ty_dec], ty_id)
otherwise -> Nothing
otherwise -> Nothing
projects / matthijs / master-project / cλash.git / blobdiff