Move around a bunch of types.

[matthijs/master-project/cλash.git] / VHDL.hs

diff --git a/VHDL.hs b/VHDL.hs
index ae7dfc9bfd42f360fa70f0beb8526770dfc5c01f..f1c7500ea032f1283d63735ba79aa348a0669a2c 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -11,7 +11,6 @@ import qualified Maybe
 import Outputable ( showSDoc, ppr )
 import qualified ForSyDe.Backend.VHDL.AST as AST
 
-
 -- | The VHDL Bit type
 bit_ty :: AST.TypeMark
 bit_ty = AST.unsafeVHDLBasicId "Bit"