import qualified Var
import qualified TyCon
import qualified DataCon
+import qualified CoreSubst
import Outputable ( showSDoc, ppr )
-- Local imports
init_session = VHDLSession Map.empty Map.empty builtin_funcs globalNameTable
(units, final_session) =
State.runState (createLibraryUnits binds) init_session
- ty_decls = Map.elems (final_session ^. vsTypes)
+ ty_decls = map (uncurry AST.TypeDec) $ Map.elems (final_session ^. vsTypes)
ieee_context = [
AST.Library $ mkVHDLBasicId "IEEE",
mkUseAll ["IEEE", "std_logic_1164"],
full_context =
mkUseAll ["work", "types"]
: ieee_context
- type_package = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") (map (AST.PDITD . snd) ty_decls)
+ type_package = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") (map AST.PDITD ty_decls)
-- Create a use foo.bar.all statement. Takes a list of components in the used
-- name. Must contain at least two components
Just t -> return t
-- No type yet, try to construct it
Nothing -> do
- let new_ty = do
- -- Use the Maybe Monad for failing when one of these fails
- (tycon, args) <- Type.splitTyConApp_maybe ty
- let name = Name.getOccString (TyCon.tyConName tycon)
- case name of
- "TFVec" -> Just $ mk_vector_ty (tfvec_len ty) ty
- "SizedWord" -> Just $ mk_vector_ty (sized_word_len ty) ty
- otherwise -> Nothing
- -- Return new_ty when a new type was successfully created
- Maybe.fromMaybe
- (error $ "Unsupported Haskell type: " ++ (showSDoc $ ppr ty))
- new_ty
+ newty_maybe <- (construct_vhdl_ty ty)
+ case newty_maybe of
+ Just (ty_id, ty_def) -> do
+ -- TODO: Check name uniqueness
+ modA vsTypes (Map.insert (OrdType ty) (ty_id, ty_def))
+ return ty_id
+ Nothing -> error $ "Unsupported Haskell type: " ++ (showSDoc $ ppr ty)
+
+-- Construct a new VHDL type for the given Haskell type.
+construct_vhdl_ty :: Type.Type -> VHDLState (Maybe (AST.TypeMark, AST.TypeDef))
+construct_vhdl_ty ty = do
+ case Type.splitTyConApp_maybe ty of
+ Just (tycon, args) -> do
+ let name = Name.getOccString (TyCon.tyConName tycon)
+ case name of
+ "TFVec" -> do
+ res <- mk_vector_ty (tfvec_len ty) ty
+ return $ Just res
+ "SizedWord" -> do
+ res <- mk_vector_ty (sized_word_len ty) ty
+ return $ Just res
+ -- Create a custom type from this tycon
+ otherwise -> mk_tycon_ty tycon args
+ Nothing -> return $ Nothing
+
+-- | Create VHDL type for a custom tycon
+mk_tycon_ty :: TyCon.TyCon -> [Type.Type] -> VHDLState (Maybe (AST.TypeMark, AST.TypeDef))
+mk_tycon_ty tycon args =
+ case TyCon.tyConDataCons tycon of
+ -- Not an algebraic type
+ [] -> error $ "Only custom algebraic types are supported: " ++ (showSDoc $ ppr tycon)
+ [dc] -> do
+ let arg_tys = DataCon.dataConRepArgTys dc
+ -- TODO: CoreSubst docs say each Subs can be applied only once. Is this a
+ -- violation? Or does it only mean not to apply it again to the same
+ -- subject?
+ let real_arg_tys = map (CoreSubst.substTy subst) arg_tys
+ elem_tys <- mapM vhdl_ty real_arg_tys
+ let elems = zipWith AST.ElementDec recordlabels elem_tys
+ -- For a single construct datatype, build a record with one field for
+ -- each argument.
+ -- TODO: Add argument type ids to this, to ensure uniqueness
+ -- TODO: Special handling for tuples?
+ let ty_id = mkVHDLExtId $ nameToString (TyCon.tyConName tycon)
+ let ty_def = AST.TDR $ AST.RecordTypeDef elems
+ return $ Just (ty_id, ty_def)
+ dcs -> error $ "Only single constructor datatypes supported: " ++ (showSDoc $ ppr tycon)
+ where
+ -- Create a subst that instantiates all types passed to the tycon
+ -- TODO: I'm not 100% sure that this is the right way to do this. It seems
+ -- to work so far, though..
+ tyvars = TyCon.tyConTyVars tycon
+ subst = CoreSubst.extendTvSubstList CoreSubst.emptySubst (zip tyvars args)
-- | Create a VHDL vector type
mk_vector_ty ::
Int -- ^ The length of the vector
-> Type.Type -- ^ The Haskell type to create a VHDL type for
- -> VHDLState AST.TypeMark -- The typemark created.
+ -> VHDLState (AST.TypeMark, AST.TypeDef) -- The typemark created.
mk_vector_ty len ty = do
-- Assume there is a single type argument
-- TODO: Use el_ty
let range = AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len - 1))]
let ty_def = AST.TDA $ AST.ConsArrayDef range std_logic_ty
- let ty_dec = AST.TypeDec ty_id ty_def
- -- TODO: Check name uniqueness
- --State.modify (Map.insert (OrdType ty) (ty_id, ty_dec))
- modA vsTypes (Map.insert (OrdType ty) (ty_id, ty_dec))
modA vsTypeFuns (Map.insert (OrdType ty) (genUnconsVectorFuns std_logic_ty ty_id))
- return ty_id
+ return (ty_id, ty_def)
builtin_types =
bndrToString = OccName.occNameString . Name.nameOccName . Var.varName
+-- Extracts the string version of the name
+nameToString :: Name.Name -> String
+nameToString = OccName.occNameString . Name.nameOccName
+
-- | A consise representation of a (set of) ports on a builtin function
--type PortMap = HsValueMap (String, AST.TypeMark)
-- | A consise representation of a builtin function
BuiltIn "hwnot" [("a", VHDL.bit_ty)] ("o", VHDL.bit_ty)
]
+recordlabels = map (\c -> mkVHDLBasicId [c]) ['A'..'Z']
+
-- | Map a port specification of a builtin function to a VHDL Signal to put in
-- a VHDLSignalMap
toVHDLSignalMapElement :: (String, AST.TypeMark) -> VHDLSignalMapElement