Put a TypeMark in a VHDLSignalmap.

[matthijs/master-project/cλash.git] / VHDL.hs

diff --git a/VHDL.hs b/VHDL.hs
index f1c7500ea032f1283d63735ba79aa348a0669a2c..df7eaf89b94facc56cf8a1aa86a8ea7ff62518ec 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -3,14 +3,86 @@
 --
 module VHDL where
 
-import Flatten
+import Data.Traversable
+import qualified Maybe
+
 import qualified Type
 import qualified Name
 import qualified TyCon
-import qualified Maybe
 import Outputable ( showSDoc, ppr )
+
 import qualified ForSyDe.Backend.VHDL.AST as AST
 
+import VHDLTypes
+import FlattenTypes
+import TranslatorTypes
+
+-- | Create an entity for a given function
+createEntity ::
+  HsFunction        -- | The function signature
+  -> FuncData       -- | The function data collected so far
+  -> FuncData       -- | The modified function data
+
+createEntity hsfunc fdata = 
+  let func = flatFunc fdata in
+  case func of
+    -- Skip (builtin) functions without a FlatFunction
+    Nothing -> fdata
+    -- Create an entity for all other functions
+    Just flatfunc ->
+      
+      let 
+        s       = sigs flatfunc
+        a       = args flatfunc
+        r       = res  flatfunc
+        args'   = map (fmap (mkMap s)) a
+        res'    = fmap (mkMap s) r
+        ent_decl' = createEntityAST hsfunc args' res'
+        entity' = Entity args' res' (Just ent_decl')
+      in
+        fdata { entity = Just entity' }
+  where
+    mkMap :: Eq id => [(id, SignalInfo)] -> id -> (AST.VHDLId, AST.TypeMark)
+    mkMap sigmap id =
+      (mkVHDLId nm, vhdl_ty ty)
+      where
+        info = Maybe.fromMaybe
+          (error $ "Signal not found in the name map? This should not happen!")
+          (lookup id sigmap)
+        nm = Maybe.fromMaybe
+          (error $ "Signal not named? This should not happen!")
+          (sigName info)
+        ty = sigTy info
+
+-- | Create the VHDL AST for an entity
+createEntityAST ::
+  HsFunction            -- | The signature of the function we're working with
+  -> [VHDLSignalMap]    -- | The entity's arguments
+  -> VHDLSignalMap      -- | The entity's result
+  -> AST.EntityDec      -- | The entity with the ent_decl filled in as well
+
+createEntityAST hsfunc args res =
+  AST.EntityDec vhdl_id ports
+  where
+    vhdl_id = mkEntityId hsfunc
+    ports = []
+
+-- | Generate a VHDL entity name for the given hsfunc
+mkEntityId hsfunc =
+  -- TODO: This doesn't work for functions with multiple signatures!
+  mkVHDLId $ hsFuncName hsfunc
+
+getLibraryUnits ::
+  (HsFunction, FuncData)      -- | A function from the session
+  -> [AST.LibraryUnit]        -- | The library units it generates
+
+getLibraryUnits (hsfunc, fdata) =
+  case entity fdata of 
+    Nothing -> []
+    Just ent -> case ent_decl ent of
+      Nothing -> []
+      Just decl -> [AST.LUEntity decl]
+
 -- | The VHDL Bit type
 bit_ty :: AST.TypeMark
 bit_ty = AST.unsafeVHDLBasicId "Bit"
@@ -36,4 +108,3 @@ vhdl_ty_maybe ty =
 -- Shortcut
 mkVHDLId :: String -> AST.VHDLId
 mkVHDLId = AST.unsafeVHDLBasicId
-