Put a TypeMark in a VHDLSignalmap.

[matthijs/master-project/cλash.git] / VHDL.hs

diff --git a/VHDL.hs b/VHDL.hs
index 956237732dd214610dbfa807074b1577b661c9e8..df7eaf89b94facc56cf8a1aa86a8ea7ff62518ec 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -37,24 +37,51 @@ createEntity hsfunc fdata =
         r       = res  flatfunc
         args'   = map (fmap (mkMap s)) a
         res'    = fmap (mkMap s) r
-        entity' = Entity args' res' Nothing
+        ent_decl' = createEntityAST hsfunc args' res'
+        entity' = Entity args' res' (Just ent_decl')
       in
         fdata { entity = Just entity' }
   where
-    mkMap :: Eq id => [(id, SignalInfo)] -> id -> AST.VHDLId
+    mkMap :: Eq id => [(id, SignalInfo)] -> id -> (AST.VHDLId, AST.TypeMark)
     mkMap sigmap id =
-      mkVHDLId nm
+      (mkVHDLId nm, vhdl_ty ty)
       where
         info = Maybe.fromMaybe
           (error $ "Signal not found in the name map? This should not happen!")
           (lookup id sigmap)
         nm = Maybe.fromMaybe
           (error $ "Signal not named? This should not happen!")
-          (name info)
-      
+          (sigName info)
+        ty = sigTy info
+
+-- | Create the VHDL AST for an entity
+createEntityAST ::
+  HsFunction            -- | The signature of the function we're working with
+  -> [VHDLSignalMap]    -- | The entity's arguments
+  -> VHDLSignalMap      -- | The entity's result
+  -> AST.EntityDec      -- | The entity with the ent_decl filled in as well
+
+createEntityAST hsfunc args res =
+  AST.EntityDec vhdl_id ports
+  where
+    vhdl_id = mkEntityId hsfunc
+    ports = []
 
+-- | Generate a VHDL entity name for the given hsfunc
+mkEntityId hsfunc =
+  -- TODO: This doesn't work for functions with multiple signatures!
+  mkVHDLId $ hsFuncName hsfunc
 
+getLibraryUnits ::
+  (HsFunction, FuncData)      -- | A function from the session
+  -> [AST.LibraryUnit]        -- | The library units it generates
 
+getLibraryUnits (hsfunc, fdata) =
+  case entity fdata of 
+    Nothing -> []
+    Just ent -> case ent_decl ent of
+      Nothing -> []
+      Just decl -> [AST.LUEntity decl]
 
 -- | The VHDL Bit type
 bit_ty :: AST.TypeMark