Put a TypeMark in a VHDLSignalmap.

[matthijs/master-project/cλash.git] / VHDL.hs

diff --git a/VHDL.hs b/VHDL.hs
index 192714778d5605c40efd37dc2cc85dc1540890f4..df7eaf89b94facc56cf8a1aa86a8ea7ff62518ec 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -42,9 +42,9 @@ createEntity hsfunc fdata =
       in
         fdata { entity = Just entity' }
   where
-    mkMap :: Eq id => [(id, SignalInfo)] -> id -> AST.VHDLId
+    mkMap :: Eq id => [(id, SignalInfo)] -> id -> (AST.VHDLId, AST.TypeMark)
     mkMap sigmap id =
-      mkVHDLId nm
+      (mkVHDLId nm, vhdl_ty ty)
       where
         info = Maybe.fromMaybe
           (error $ "Signal not found in the name map? This should not happen!")
@@ -52,6 +52,7 @@ createEntity hsfunc fdata =
         nm = Maybe.fromMaybe
           (error $ "Signal not named? This should not happen!")
           (sigName info)
+        ty = sigTy info
 
 -- | Create the VHDL AST for an entity
 createEntityAST ::