Put a TypeMark in a VHDLSignalmap.

[matthijs/master-project/cλash.git] / VHDL.hs

diff --git a/VHDL.hs b/VHDL.hs
index 0387327c05d2c02f4503c4990e6d742200d4b009..df7eaf89b94facc56cf8a1aa86a8ea7ff62518ec 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -42,16 +42,17 @@ createEntity hsfunc fdata =
       in
         fdata { entity = Just entity' }
   where
-    mkMap :: Eq id => [(id, SignalInfo)] -> id -> AST.VHDLId
+    mkMap :: Eq id => [(id, SignalInfo)] -> id -> (AST.VHDLId, AST.TypeMark)
     mkMap sigmap id =
-      mkVHDLId nm
+      (mkVHDLId nm, vhdl_ty ty)
       where
         info = Maybe.fromMaybe
           (error $ "Signal not found in the name map? This should not happen!")
           (lookup id sigmap)
         nm = Maybe.fromMaybe
           (error $ "Signal not named? This should not happen!")
-          (name info)
+          (sigName info)
+        ty = sigTy info
 
 -- | Create the VHDL AST for an entity
 createEntityAST ::
@@ -71,6 +72,16 @@ mkEntityId hsfunc =
   -- TODO: This doesn't work for functions with multiple signatures!
   mkVHDLId $ hsFuncName hsfunc
 
+getLibraryUnits ::
+  (HsFunction, FuncData)      -- | A function from the session
+  -> [AST.LibraryUnit]        -- | The library units it generates
+
+getLibraryUnits (hsfunc, fdata) =
+  case entity fdata of 
+    Nothing -> []
+    Just ent -> case ent_decl ent of
+      Nothing -> []
+      Just decl -> [AST.LUEntity decl]
 
 -- | The VHDL Bit type
 bit_ty :: AST.TypeMark