import qualified Control.Monad.Trans.State as State
import qualified Data.Monoid as Monoid
import Data.Accessor
+import Data.Accessor.MonadState as MonadState
import Debug.Trace
-- ForSyDe
map (Arrow.second $ AST.DesignFile full_context) units
where
- init_session = VHDLState Map.empty Map.empty Map.empty Map.empty
+ init_session = VHDLState emptyTypeState Map.empty
(units, final_session) =
State.runState (createLibraryUnits binds) init_session
- tyfun_decls = map snd $ Map.elems (final_session ^.vsTypeFuns)
- ty_decls = map mktydecl $ Map.elems (final_session ^. vsTypes)
- vec_decls = map (\(v_id, v_def) -> AST.PDITD $ AST.TypeDec v_id v_def) (Map.elems (final_session ^. vsElemTypes))
+ tyfun_decls = map snd $ Map.elems (final_session ^. vsType ^. vsTypeFuns)
+ ty_decls = final_session ^. vsType ^. vsTypeDecls
tfvec_index_decl = AST.PDISD $ AST.SubtypeDec tfvec_indexTM tfvec_index_def
tfvec_range = AST.ConstraintRange $ AST.SubTypeRange (AST.PrimLit "-1") (AST.PrimName $ AST.NAttribute $ AST.AttribName (AST.NSimple integerTM) highId Nothing)
tfvec_index_def = AST.SubtypeIn integerTM (Just tfvec_range)
mkUseAll ["work", "types"]
: (mkUseAll ["work"]
: ieee_context)
- type_package_dec = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") ([tfvec_index_decl] ++ vec_decls ++ ty_decls ++ subProgSpecs)
+ type_package_dec = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") ([tfvec_index_decl] ++ ty_decls ++ subProgSpecs)
type_package_body = AST.LUPackageBody $ AST.PackageBody typesId tyfun_decls
subProgSpecs = map subProgSpec tyfun_decls
subProgSpec = \(AST.SubProgBody spec _ _) -> AST.PDISS spec
- mktydecl :: (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn) -> AST.PackageDecItem
- mktydecl (ty_id, Left ty_def) = AST.PDITD $ AST.TypeDec ty_id ty_def
- mktydecl (ty_id, Right ty_def) = AST.PDISD $ AST.SubtypeDec ty_id ty_def
-- Create a use foo.bar.all statement. Takes a list of components in the used
-- name. Must contain at least two components
ty = Var.varType bndr
error_msg = "\nVHDL.createEntity.mkMap: Can not create entity: " ++ pprString fname ++ "\nbecause no type can be created for port: " ++ pprString bndr
in do
- type_mark <- vhdl_ty error_msg ty
+ type_mark <- MonadState.lift vsType $ vhdl_ty error_msg ty
return (id, type_mark)
)
mkSigDec bndr =
if True then do --isInternalSigUse use || isStateSigUse use then do
let error_msg = "\nVHDL.mkSigDec: Can not make signal declaration for type: \n" ++ pprString bndr
- type_mark <- (vhdl_ty error_msg) $ Var.varType bndr
+ type_mark <- MonadState.lift vsType $ vhdl_ty error_msg (Var.varType bndr)
return $ Just (AST.SigDec (varToVHDLId bndr) type_mark Nothing)
else
return Nothing
(DataAlt dc, bndrs, (Var sel_bndr)) -> do
case List.elemIndex sel_bndr bndrs of
Just i -> do
- labels <- getFieldLabels (Id.idType scrut)
+ labels <- MonadState.lift vsType $ getFieldLabels (Id.idType scrut)
let label = labels!!i
let sel_name = mkSelectedName (varToVHDLName scrut) label
let sel_expr = AST.PrimName sel_name