-> [(AST.VHDLId, AST.DesignFile)]
createDesignFiles flatfuncmap =
- -- TODO: Output types
- (mkVHDLId "types", AST.DesignFile [] [type_package]) :
- map (Arrow.second $ AST.DesignFile context) units
+ (mkVHDLId "types", AST.DesignFile ieee_context [type_package]) :
+ map (Arrow.second $ AST.DesignFile full_context) units
where
init_session = VHDLSession Map.empty builtin_funcs
(units, final_session) =
State.runState (createLibraryUnits flatfuncmap) init_session
ty_decls = Map.elems (final_session ^. vsTypes)
- context = [
- AST.Library $ mkVHDLId "IEEE",
- AST.Use $ (AST.NSimple $ mkVHDLId "IEEE.std_logic_1164") AST.:.: AST.All,
- AST.Use $ (AST.NSimple $ mkVHDLId "work.types") AST.:.: AST.All]
+ ieee_context = [
+ AST.Library $ mkVHDLId "IEEE",
+ AST.Use $ (AST.NSimple $ mkVHDLId "IEEE.std_logic_1164") AST.:.: AST.All
+ ]
+ full_context =
+ (AST.Use $ (AST.NSimple $ mkVHDLId "work.types") AST.:.: AST.All)
+ : ieee_context
type_package = AST.LUPackageDec $ AST.PackageDec (mkVHDLId "types") (map (AST.PDITD . snd) ty_decls)
createLibraryUnits ::
args = flat_args flatfunc
res = flat_res flatfunc
defs = flat_defs flatfunc
- -- TODO: Unique ty_decls
- -- TODO: Store ty_decls somewhere
procs = map mkStateProcSm (makeStatePairs flatfunc)
procs' = map AST.CSPSm procs
-- mkSigDec only uses vsTypes from the state
let range = AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "16")]
let ty_def = AST.TDA $ AST.ConsArrayDef range std_logic_ty
let ty_dec = AST.TypeDec ty_id ty_def
+ -- TODO: Check name uniqueness
State.modify (Map.insert (OrdType ty) (ty_id, ty_dec))
return ty_id