import qualified Data.Foldable as Foldable
import qualified Data.List as List
+import qualified Data.Map as Map
import qualified Maybe
import qualified Control.Monad as Monad
import qualified Control.Arrow as Arrow
+import qualified Control.Monad.Trans.State as State
import qualified Data.Traversable as Traversable
import qualified Data.Monoid as Monoid
+import Data.Accessor
import qualified Type
import qualified TysWiredIn
import TranslatorTypes
import Pretty
-getDesignFiles :: [FuncData] -> [AST.DesignFile]
-getDesignFiles funcs =
- map (AST.DesignFile context) units
+createDesignFiles ::
+ FlatFuncMap
+ -> [(AST.VHDLId, AST.DesignFile)]
+
+createDesignFiles flatfuncmap =
+ -- TODO: Output types
+ map (Arrow.second $ AST.DesignFile context) units
where
- units = filter (not.null) $ map getLibraryUnits funcs
+ init_session = VHDLSession Map.empty Map.empty
+ (units, final_session) =
+ State.runState (createLibraryUnits flatfuncmap) init_session
context = [
AST.Library $ mkVHDLId "IEEE",
AST.Use $ (AST.NSimple $ mkVHDLId "IEEE.std_logic_1164") AST.:.: AST.All]
-
+
+createLibraryUnits ::
+ FlatFuncMap
+ -> VHDLState [(AST.VHDLId, [AST.LibraryUnit])]
+
+createLibraryUnits flatfuncmap = do
+ let hsfuncs = Map.keys flatfuncmap
+ let flatfuncs = Map.elems flatfuncmap
+ entities <- Monad.zipWithM createEntity hsfuncs flatfuncs
+ archs <- Monad.zipWithM createArchitecture hsfuncs flatfuncs
+ return $ zipWith
+ (\ent arch ->
+ let AST.EntityDec id _ = ent in
+ (id, [AST.LUEntity ent, AST.LUArch arch])
+ )
+ entities archs
+
-- | Create an entity for a given function
createEntity ::
- HsFunction -- | The function signature
- -> FuncData -- | The function data collected so far
- -> VHDLState ()
-
-createEntity hsfunc fdata =
- let func = flatFunc fdata in
- case func of
- -- Skip (builtin) functions without a FlatFunction
- Nothing -> do return ()
- -- Create an entity for all other functions
- Just flatfunc ->
+ HsFunction -- | The function signature
+ -> FlatFunction -- | The FlatFunction
+ -> VHDLState AST.EntityDec -- | The resulting entity
+
+createEntity hsfunc flatfunc =
let
sigs = flat_sigs flatfunc
args = flat_args flatfunc
pkg_decl = if null ty_decls && null ty_decls'
then Nothing
else Just $ AST.PackageDec pkg_id (map AST.PDITD $ ty_decls ++ ty_decls')
+ -- TODO: Output package
AST.EntityDec entity_id _ = ent_decl'
- entity' = Entity entity_id args' res' (Just ent_decl') pkg_decl
+ signature = Entity entity_id args' res'
in do
- setEntity hsfunc entity'
+ modA vsSignatures (Map.insert hsfunc signature)
+ return ent_decl'
where
mkMap ::
[(SignalId, SignalInfo)]
-- | Create an architecture for a given function
createArchitecture ::
- HsFunction -- | The function signature
- -> FuncData -- | The function data collected so far
- -> VHDLState ()
-
-createArchitecture hsfunc fdata =
- let func = flatFunc fdata in
- case func of
- -- Skip (builtin) functions without a FlatFunction
- Nothing -> do return ()
- -- Create an architecture for all other functions
- Just flatfunc -> do
- let sigs = flat_sigs flatfunc
- let args = flat_args flatfunc
- let res = flat_res flatfunc
- let defs = flat_defs flatfunc
- let entity_id = Maybe.fromMaybe
- (error $ "Building architecture without an entity? This should not happen!")
- (getEntityId fdata)
- -- Create signal declarations for all signals that are not in args and
- -- res
- let (ty_decls, sig_decs) = Arrow.second Maybe.catMaybes $ Traversable.traverse (mkSigDec . snd) sigs
- -- TODO: Unique ty_decls
- -- TODO: Store ty_decls somewhere
- -- Create concurrent statements for all signal definitions
- statements <- mapM (mkConcSm sigs) defs
- let procs = map mkStateProcSm (makeStatePairs flatfunc)
- let procs' = map AST.CSPSm procs
- let arch = AST.ArchBody (mkVHDLId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs')
- setArchitecture hsfunc arch
+ HsFunction -- ^ The function signature
+ -> FlatFunction -- ^ The FlatFunction
+ -> VHDLState AST.ArchBody -- ^ The architecture for this function
+
+createArchitecture hsfunc flatfunc = do
+ signaturemap <- getA vsSignatures
+ let signature = Maybe.fromMaybe
+ (error $ "Generating architecture for function " ++ (prettyShow hsfunc) ++ "without signature? This should not happen!")
+ (Map.lookup hsfunc signaturemap)
+ let entity_id = ent_id signature
+ -- Create concurrent statements for all signal definitions
+ let statements = zipWith (mkConcSm signaturemap sigs) defs [0..]
+ return $ AST.ArchBody (mkVHDLId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs')
+ where
+ sigs = flat_sigs flatfunc
+ args = flat_args flatfunc
+ res = flat_res flatfunc
+ defs = flat_defs flatfunc
+ -- Create signal declarations for all internal and state signals
+ (ty_decls, sig_decs) = Arrow.second Maybe.catMaybes $ Traversable.traverse (mkSigDec . snd) sigs
+ -- TODO: Unique ty_decls
+ -- TODO: Store ty_decls somewhere
+ procs = map mkStateProcSm (makeStatePairs flatfunc)
+ procs' = map AST.CSPSm procs
-- | Looks up all pairs of old state, new state signals, together with
-- the state id they represent.
-- | Transforms a signal definition into a VHDL concurrent statement
mkConcSm ::
- [(SignalId, SignalInfo)] -- | The signals in the current architecture
- -> SigDef -- | The signal definition
- -> VHDLState AST.ConcSm -- | The corresponding VHDL component instantiation.
-
-mkConcSm sigs (FApp hsfunc args res) = do
- fdata_maybe <- getFunc hsfunc
- let fdata = Maybe.fromMaybe
- (error $ "Using function '" ++ (prettyShow hsfunc) ++ "' that is not in the session? This should not happen!")
- fdata_maybe
- let entity = Maybe.fromMaybe
- (error $ "Using function '" ++ (prettyShow hsfunc) ++ "' without entity declaration? This should not happen!")
- (funcEntity fdata)
- let entity_id = ent_id entity
- label <- uniqueName (AST.fromVHDLId entity_id)
- -- Add a clk port if we have state
- let clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLId "clk") "clk"
- let portmaps = mkAssocElems sigs args res entity ++ (if hasState hsfunc then [clk_port] else [])
- return $ AST.CSISm $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
-
-mkConcSm sigs (UncondDef src dst) = do
- let src_expr = vhdl_expr src
- let src_wform = AST.Wform [AST.WformElem src_expr Nothing]
- let dst_name = AST.NSimple (getSignalId $ signalInfo sigs dst)
- let assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
- return $ AST.CSSASm assign
+ SignatureMap -- ^ The interfaces of functions in the session
+ -> [(SignalId, SignalInfo)] -- ^ The signals in the current architecture
+ -> SigDef -- ^ The signal definition
+ -> Int -- ^ A number that will be unique for all
+ -- concurrent statements in the architecture.
+ -> AST.ConcSm -- ^ The corresponding VHDL component instantiation.
+
+mkConcSm signatures sigs (FApp hsfunc args res) num =
+ let
+ signature = Maybe.fromMaybe
+ (error $ "Using function '" ++ (prettyShow hsfunc) ++ "' without signature? This should not happen!")
+ (Map.lookup hsfunc signatures)
+ entity_id = ent_id signature
+ label = (AST.fromVHDLId entity_id) ++ "_" ++ (show num)
+ -- Add a clk port if we have state
+ clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLId "clk") "clk"
+ portmaps = mkAssocElems sigs args res signature ++ (if hasState hsfunc then [clk_port] else [])
+ in
+ AST.CSISm $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
+
+mkConcSm _ sigs (UncondDef src dst) _ =
+ let
+ src_expr = vhdl_expr src
+ src_wform = AST.Wform [AST.WformElem src_expr Nothing]
+ dst_name = AST.NSimple (getSignalId $ signalInfo sigs dst)
+ assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
+ in
+ AST.CSSASm assign
where
vhdl_expr (Left id) = mkIdExpr sigs id
vhdl_expr (Right expr) =
(Eq a b) ->
(mkIdExpr sigs a) AST.:=: (mkIdExpr sigs b)
-mkConcSm sigs (CondDef cond true false dst) = do
- let cond_expr = mkIdExpr sigs cond
- let true_expr = mkIdExpr sigs true
- let false_expr = mkIdExpr sigs false
- let false_wform = AST.Wform [AST.WformElem false_expr Nothing]
- let true_wform = AST.Wform [AST.WformElem true_expr Nothing]
- let whenelse = AST.WhenElse true_wform cond_expr
- let dst_name = AST.NSimple (getSignalId $ signalInfo sigs dst)
- let assign = dst_name AST.:<==: (AST.ConWforms [whenelse] false_wform Nothing)
- return $ AST.CSSASm assign
+mkConcSm _ sigs (CondDef cond true false dst) _ =
+ let
+ cond_expr = mkIdExpr sigs cond
+ true_expr = mkIdExpr sigs true
+ false_expr = mkIdExpr sigs false
+ false_wform = AST.Wform [AST.WformElem false_expr Nothing]
+ true_wform = AST.Wform [AST.WformElem true_expr Nothing]
+ whenelse = AST.WhenElse true_wform cond_expr
+ dst_name = AST.NSimple (getSignalId $ signalInfo sigs dst)
+ assign = dst_name AST.:<==: (AST.ConWforms [whenelse] false_wform Nothing)
+ in
+ AST.CSSASm assign
-- | Turn a SignalId into a VHDL Expr
mkIdExpr :: [(SignalId, SignalInfo)] -> SignalId -> AST.Expr
mkAssocElem (Just port) signal = Just $ Just port AST.:=>: (AST.ADName (AST.NSimple (mkVHDLId signal)))
mkAssocElem Nothing _ = Nothing
--- | Extracts the generated entity id from the given funcdata
-getEntityId :: FuncData -> Maybe AST.VHDLId
-getEntityId fdata =
- case funcEntity fdata of
- Nothing -> Nothing
- Just e -> case ent_decl e of
- Nothing -> Nothing
- Just (AST.EntityDec id _) -> Just id
-
-getLibraryUnits ::
- FuncData -- | A function from the session
- -> [AST.LibraryUnit] -- | The entity, architecture and optional package for the function
-
-getLibraryUnits fdata =
- case funcEntity fdata of
- Nothing -> []
- Just ent ->
- case ent_decl ent of
- Nothing -> []
- Just decl ->
- case funcArch fdata of
- Nothing -> []
- Just arch ->
- [AST.LUEntity decl, AST.LUArch arch]
- ++ (Maybe.maybeToList (fmap AST.LUPackageDec $ ent_pkg_decl ent))
-
-- | The VHDL Bit type
bit_ty :: AST.TypeMark
bit_ty = AST.unsafeVHDLBasicId "Bit"
projects / matthijs / master-project / cλash.git / blobdiff