import qualified Control.Monad as Monad
import qualified Type
+import qualified TysWiredIn
import qualified Name
import qualified TyCon
import Outputable ( showSDoc, ppr )
import TranslatorTypes
import Pretty
-getDesignFile :: VHDLState AST.DesignFile
-getDesignFile = do
+getDesignFiles :: VHDLState [AST.DesignFile]
+getDesignFiles = do
-- Extract the library units generated from all the functions in the
-- session.
funcs <- getFuncs
- let units = concat $ map getLibraryUnits funcs
+ let units = Maybe.mapMaybe getLibraryUnits funcs
let context = [
AST.Library $ mkVHDLId "IEEE",
AST.Use $ (AST.NSimple $ mkVHDLId "IEEE.std_logic_1164") AST.:.: AST.All]
- return $ AST.DesignFile
- context
- units
+ return $ map (\(ent, arch) -> AST.DesignFile context [ent, arch]) units
-- | Create an entity for a given function
createEntity ::
let sig_decs = Maybe.catMaybes $ map (mkSigDec . snd) sigs
-- Create concurrent statements for all signal definitions
statements <- mapM (mkConcSm sigs) defs
- let procs = map mkStateProcSm (getOwnStates hsfunc flatfunc)
+ let procs = map mkStateProcSm (makeStatePairs flatfunc)
let procs' = map AST.CSPSm procs
let arch = AST.ArchBody (mkVHDLId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs')
setArchitecture hsfunc arch
+-- | Looks up all pairs of old state, new state signals, together with
+-- the state id they represent.
+makeStatePairs :: FlatFunction -> [(StateId, SignalInfo, SignalInfo)]
+makeStatePairs flatfunc =
+ [(Maybe.fromJust $ oldStateId $ sigUse old_info, old_info, new_info)
+ | old_info <- map snd (flat_sigs flatfunc)
+ , new_info <- map snd (flat_sigs flatfunc)
+ -- old_info must be an old state (and, because of the next equality,
+ -- new_info must be a new state).
+ , Maybe.isJust $ oldStateId $ sigUse old_info
+ -- And the state numbers must match
+ , (oldStateId $ sigUse old_info) == (newStateId $ sigUse new_info)]
+
+ -- Replace the second tuple element with the corresponding SignalInfo
+ --args_states = map (Arrow.second $ signalInfo sigs) args
mkStateProcSm :: (StateId, SignalInfo, SignalInfo) -> AST.ProcSm
mkStateProcSm (num, old, new) =
AST.ProcSm label [clk] [statement]
let portmaps = mkAssocElems sigs args res entity
return $ AST.CSISm $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
+mkConcSm sigs (UncondDef src dst) = do
+ let src_expr = vhdl_expr src
+ let src_wform = AST.Wform [AST.WformElem src_expr Nothing]
+ let dst_name = AST.NSimple (getSignalId $ signalInfo sigs dst)
+ let assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
+ return $ AST.CSSASm assign
+ where
+ vhdl_expr (Left id) = mkIdExpr sigs id
+ vhdl_expr (Right expr) =
+ case expr of
+ (EqLit id lit) ->
+ (mkIdExpr sigs id) AST.:=: (AST.PrimLit lit)
+ (Literal lit) ->
+ AST.PrimLit lit
+ (Eq a b) ->
+ (mkIdExpr sigs a) AST.:=: (mkIdExpr sigs b)
+
+mkConcSm sigs (CondDef cond true false dst) = do
+ let cond_expr = mkIdExpr sigs cond
+ let true_expr = mkIdExpr sigs true
+ let false_expr = mkIdExpr sigs false
+ let false_wform = AST.Wform [AST.WformElem false_expr Nothing]
+ let true_wform = AST.Wform [AST.WformElem true_expr Nothing]
+ let whenelse = AST.WhenElse true_wform cond_expr
+ let dst_name = AST.NSimple (getSignalId $ signalInfo sigs dst)
+ let assign = dst_name AST.:<==: (AST.ConWforms [whenelse] false_wform Nothing)
+ return $ AST.CSSASm assign
+
+-- | Turn a SignalId into a VHDL Expr
+mkIdExpr :: [(SignalId, SignalInfo)] -> SignalId -> AST.Expr
+mkIdExpr sigs id =
+ let src_name = AST.NSimple (getSignalId $ signalInfo sigs id) in
+ AST.PrimName src_name
+
mkAssocElems ::
[(SignalId, SignalInfo)] -- | The signals in the current architecture
-> [SignalMap] -- | The signals that are applied to function
getLibraryUnits ::
(HsFunction, FuncData) -- | A function from the session
- -> [AST.LibraryUnit] -- | The library units it generates
+ -> Maybe (AST.LibraryUnit, AST.LibraryUnit) -- | The entity and architecture for the function
getLibraryUnits (hsfunc, fdata) =
case funcEntity fdata of
- Nothing -> []
- Just ent -> case ent_decl ent of
- Nothing -> []
- Just decl -> [AST.LUEntity decl]
- ++
- case funcArch fdata of
- Nothing -> []
- Just arch -> [AST.LUArch arch]
+ Nothing -> Nothing
+ Just ent ->
+ case ent_decl ent of
+ Nothing -> Nothing
+ Just decl ->
+ case funcArch fdata of
+ Nothing -> Nothing
+ Just arch ->
+ Just (AST.LUEntity decl, AST.LUArch arch)
-- | The VHDL Bit type
bit_ty :: AST.TypeMark
bit_ty = AST.unsafeVHDLBasicId "Bit"
+-- | The VHDL Boolean type
+bool_ty :: AST.TypeMark
+bool_ty = AST.unsafeVHDLBasicId "Boolean"
+
-- | The VHDL std_logic
std_logic_ty :: AST.TypeMark
std_logic_ty = AST.unsafeVHDLBasicId "std_logic"
-- Translate a Haskell type to a VHDL type
vhdl_ty_maybe :: Type.Type -> Maybe AST.TypeMark
vhdl_ty_maybe ty =
- case Type.splitTyConApp_maybe ty of
- Just (tycon, args) ->
- let name = TyCon.tyConName tycon in
- -- TODO: Do something more robust than string matching
- case Name.getOccString name of
- "Bit" -> Just bit_ty
- otherwise -> Nothing
- otherwise -> Nothing
+ if Type.coreEqType ty TysWiredIn.boolTy
+ then
+ Just bool_ty
+ else
+ case Type.splitTyConApp_maybe ty of
+ Just (tycon, args) ->
+ let name = TyCon.tyConName tycon in
+ -- TODO: Do something more robust than string matching
+ case Name.getOccString name of
+ "Bit" -> Just std_logic_ty
+ otherwise -> Nothing
+ otherwise -> Nothing
-- Shortcut
mkVHDLId :: String -> AST.VHDLId
-mkVHDLId = AST.unsafeVHDLBasicId
+mkVHDLId s =
+ AST.unsafeVHDLBasicId s'
+ where
+ -- Strip invalid characters.
+ s' = filter (`elem` ['A'..'Z'] ++ ['a'..'z'] ++ ['0'..'9'] ++ "_.") s
projects / matthijs / master-project / cλash.git / blobdiff