createDesignFiles flatfuncmap =
-- TODO: Output types
- (mkVHDLId "types", AST.DesignFile [] [type_package]) :
- map (Arrow.second $ AST.DesignFile context) units
+ (mkVHDLId "types", AST.DesignFile ieee_context [type_package]) :
+ map (Arrow.second $ AST.DesignFile full_context) units
where
init_session = VHDLSession Map.empty builtin_funcs
(units, final_session) =
State.runState (createLibraryUnits flatfuncmap) init_session
ty_decls = Map.elems (final_session ^. vsTypes)
- context = [
- AST.Library $ mkVHDLId "IEEE",
- AST.Use $ (AST.NSimple $ mkVHDLId "IEEE.std_logic_1164") AST.:.: AST.All,
- AST.Use $ (AST.NSimple $ mkVHDLId "work.types") AST.:.: AST.All]
+ ieee_context = [
+ AST.Library $ mkVHDLId "IEEE",
+ AST.Use $ (AST.NSimple $ mkVHDLId "IEEE.std_logic_1164") AST.:.: AST.All
+ ]
+ full_context =
+ (AST.Use $ (AST.NSimple $ mkVHDLId "work.types") AST.:.: AST.All)
+ : ieee_context
type_package = AST.LUPackageDec $ AST.PackageDec (mkVHDLId "types") (map (AST.PDITD . snd) ty_decls)
createLibraryUnits ::
-- Assume there are two type arguments
let [len, el_ty] = args
-- TODO: Find actual number
- let ty_id = mkVHDLId ("vector_" ++ (show len))
+ -- Construct the type id, but filter out dots (since these are not allowed).
+ let ty_id = mkVHDLId $ filter (/='.') ("vector_" ++ (show len))
-- TODO: Use el_ty
let range = AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "16")]
let ty_def = AST.TDA $ AST.ConsArrayDef range std_logic_ty