Add name hints to various signals generated.

[matthijs/master-project/cλash.git] / VHDL.hs

diff --git a/VHDL.hs b/VHDL.hs
index b85d6ff0be288e7db0ec57ca886fae79cbc6ec09..4ab3be33ec2ba1a9a4647d62703e0efb801c811d 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -320,10 +320,14 @@ vhdl_ty_maybe ty =
           let name = TyCon.tyConName tycon in
             -- TODO: Do something more robust than string matching
             case Name.getOccString name of
-              "Bit"      -> Just bit_ty
+              "Bit"      -> Just std_logic_ty
               otherwise  -> Nothing
         otherwise -> Nothing
 
 -- Shortcut
 mkVHDLId :: String -> AST.VHDLId
-mkVHDLId = AST.unsafeVHDLBasicId
+mkVHDLId s = 
+  AST.unsafeVHDLBasicId s'
+  where
+    -- Strip invalid characters.
+    s' = filter (`elem` ['a'..'z'] ++ ['0'..'9'] ++ ['_']) s