import TranslatorTypes
import Pretty
+getDesignFile :: VHDLState AST.DesignFile
+getDesignFile = do
+ -- Extract the library units generated from all the functions in the
+ -- session.
+ funcs <- getFuncs
+ let units = concat $ map getLibraryUnits funcs
+ let context = [
+ AST.Library $ mkVHDLId "IEEE",
+ AST.Use $ (AST.NSimple $ mkVHDLId "IEEE.std_logic_1164") AST.:.: AST.All]
+ return $ AST.DesignFile
+ context
+ units
+
-- | Create an entity for a given function
createEntity ::
HsFunction -- | The function signature
in
setEntity hsfunc entity'
where
- mkMap :: Eq id => [(id, SignalInfo)] -> id -> (AST.VHDLId, AST.TypeMark)
+ mkMap :: Eq id => [(id, SignalInfo)] -> id -> Maybe (AST.VHDLId, AST.TypeMark)
mkMap sigmap id =
- (mkVHDLId nm, vhdl_ty ty)
+ if isPortSigUse $ sigUse info
+ then
+ Just (mkVHDLId nm, vhdl_ty ty)
+ else
+ Nothing
where
info = Maybe.fromMaybe
(error $ "Signal not found in the name map? This should not happen!")
(sigName info)
ty = sigTy info
--- | Create the VHDL AST for an entity
+ -- | Create the VHDL AST for an entity
createEntityAST ::
HsFunction -- | The signature of the function we're working with
-> [VHDLSignalMap] -- | The entity's arguments
vhdl_id = mkEntityId hsfunc
ports = concatMap (mapToPorts AST.In) args
++ mapToPorts AST.Out res
+ ++ clk_port
mapToPorts :: AST.Mode -> VHDLSignalMap -> [AST.IfaceSigDec]
mapToPorts mode m =
- map (mkIfaceSigDec mode) (Foldable.toList m)
+ Maybe.catMaybes $ map (mkIfaceSigDec mode) (Foldable.toList m)
+ -- Add a clk port if we have state
+ clk_port = if hasState hsfunc
+ then
+ [AST.IfaceSigDec (mkVHDLId "clk") AST.In VHDL.std_logic_ty]
+ else
+ []
-- | Create a port declaration
mkIfaceSigDec ::
AST.Mode -- | The mode for the port (In / Out)
- -> (AST.VHDLId, AST.TypeMark) -- | The id and type for the port
- -> AST.IfaceSigDec -- | The resulting port declaration
+ -> Maybe (AST.VHDLId, AST.TypeMark) -- | The id and type for the port
+ -> Maybe AST.IfaceSigDec -- | The resulting port declaration
-mkIfaceSigDec mode (id, ty) = AST.IfaceSigDec id mode ty
+mkIfaceSigDec mode (Just (id, ty)) = Just $ AST.IfaceSigDec id mode ty
+mkIfaceSigDec _ Nothing = Nothing
-- | Generate a VHDL entity name for the given hsfunc
mkEntityId hsfunc =
(getEntityId fdata)
-- Create signal declarations for all signals that are not in args and
-- res
- let sig_decs = [mkSigDec info | (id, info) <- sigs, (all (id `Foldable.notElem`) (res:args)) ]
+ let sig_decs = Maybe.catMaybes $ map (mkSigDec . snd) sigs
-- Create component instantiations for all function applications
insts <- mapM (mkCompInsSm sigs) apps
let procs = map mkStateProcSm (getOwnStates hsfunc flatfunc)
rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clk)]
statement = AST.IfSm rising_edge_clk [assign] [] Nothing
-mkSigDec :: SignalInfo -> AST.SigDec
+mkSigDec :: SignalInfo -> Maybe AST.SigDec
mkSigDec info =
- AST.SigDec (getSignalId info) (vhdl_ty ty) Nothing
+ let use = sigUse info in
+ if isInternalSigUse use || isStateSigUse use then
+ Just $ AST.SigDec (getSignalId info) (vhdl_ty ty) Nothing
+ else
+ Nothing
where
ty = sigTy info
-- | Transforms a flat function application to a VHDL component instantiation.
mkCompInsSm ::
- [(UnnamedSignal, SignalInfo)] -- | The signals in the current architecture
- -> FApp UnnamedSignal -- | The application to look at.
+ [(SignalId, SignalInfo)] -- | The signals in the current architecture
+ -> FApp -- | The application to look at.
-> VHDLState AST.CompInsSm -- | The corresponding VHDL component instantiation.
mkCompInsSm sigs app = do
return $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
mkAssocElems ::
- [(UnnamedSignal, SignalInfo)] -- | The signals in the current architecture
- -> FApp UnnamedSignal -- | The application to look at.
+ [(SignalId, SignalInfo)] -- | The signals in the current architecture
+ -> FApp -- | The application to look at.
-> Entity -- | The entity to map against.
-> [AST.AssocElem] -- | The resulting port maps
mkAssocElems sigmap app entity =
-- Create the actual AssocElems
- zipWith mkAssocElem ports sigs
+ Maybe.catMaybes $ zipWith mkAssocElem ports sigs
where
-- Turn the ports and signals from a map into a flat list. This works,
-- since the maps must have an identical form by definition. TODO: Check
arg_sigs = (concat (map Foldable.toList (appArgs app)))
res_sigs = Foldable.toList (appRes app)
-- Extract the id part from the (id, type) tuple
- ports = (map fst (arg_ports ++ res_ports))
+ ports = (map (fmap fst) (arg_ports ++ res_ports))
-- Translate signal numbers into names
sigs = (map (lookupSigName sigmap) (arg_sigs ++ res_sigs))
-- | Look up a signal in the signal name map
-lookupSigName :: [(UnnamedSignal, SignalInfo)] -> UnnamedSignal -> String
+lookupSigName :: [(SignalId, SignalInfo)] -> SignalId -> String
lookupSigName sigs sig = name
where
info = Maybe.fromMaybe
(sigName info)
-- | Create an VHDL port -> signal association
-mkAssocElem :: AST.VHDLId -> String -> AST.AssocElem
-mkAssocElem port signal = Just port AST.:=>: (AST.ADName (AST.NSimple (mkVHDLId signal)))
+mkAssocElem :: Maybe AST.VHDLId -> String -> Maybe AST.AssocElem
+mkAssocElem (Just port) signal = Just $ Just port AST.:=>: (AST.ADName (AST.NSimple (mkVHDLId signal)))
+mkAssocElem Nothing _ = Nothing
-- | Extracts the generated entity id from the given funcdata
getEntityId :: FuncData -> Maybe AST.VHDLId
bit_ty :: AST.TypeMark
bit_ty = AST.unsafeVHDLBasicId "Bit"
+-- | The VHDL std_logic
+std_logic_ty :: AST.TypeMark
+std_logic_ty = AST.unsafeVHDLBasicId "std_logic"
+
-- Translate a Haskell type to a VHDL type
vhdl_ty :: Type.Type -> AST.TypeMark
vhdl_ty ty = Maybe.fromMaybe
projects / matthijs / master-project / cλash.git / blobdiff