Add a Type to a Literal SignalExpr.

[matthijs/master-project/cλash.git] / VHDL.hs

diff --git a/VHDL.hs b/VHDL.hs
index 1d605ea7de71b1279ce051e5f675eb1aa7c193c8..08034192bf6ced1d4e813f094c4be9b3cbf3417c 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -50,7 +50,8 @@ createDesignFiles flatfuncmap =
     ty_decls = Map.elems (final_session ^. vsTypes)
     ieee_context = [
         AST.Library $ mkVHDLBasicId "IEEE",
-        mkUseAll ["IEEE", "std_logic_1164"]
+        mkUseAll ["IEEE", "std_logic_1164"],
+        mkUseAll ["IEEE", "numeric_std"]
       ]
     full_context =
       mkUseAll ["work", "types"]
@@ -274,7 +275,7 @@ mkConcSm _ sigs (UncondDef src dst) _ =
       case expr of
         (EqLit id lit) ->
           (mkIdExpr sigs id) AST.:=: (AST.PrimLit lit)
-        (Literal lit) ->
+        (Literal lit _) ->
           AST.PrimLit lit
         (Eq a b) ->
           (mkIdExpr sigs a) AST.:=: (mkIdExpr sigs b)
@@ -369,7 +370,7 @@ vhdl_ty ty = do
             (tycon, args) <- Type.splitTyConApp_maybe ty
             let name = Name.getOccString (TyCon.tyConName tycon)
             case name of
-              "FSVec" -> Just $ mk_fsvec_ty ty args
+              "FSVec" -> Just $ mk_vector_ty (fsvec_len ty) ty
               "SizedWord" -> Just $ mk_vector_ty (sized_word_len ty) ty
               otherwise -> Nothing
       -- Return new_ty when a new type was successfully created
@@ -377,25 +378,6 @@ vhdl_ty ty = do
         (error $ "Unsupported Haskell type: " ++ (showSDoc $ ppr ty))
         new_ty
 
--- | Create a VHDL type belonging to a FSVec Haskell type
-mk_fsvec_ty ::
-  Type.Type -- ^ The Haskell type to create a VHDL type for
-  -> [Type.Type] -- ^ Type arguments to the FSVec type constructor
-  -> TypeState AST.TypeMark -- The typemark created.
-
-mk_fsvec_ty ty args = do
-  -- Assume there are two type arguments
-  let [len, el_ty] = args 
-  let len_int = eval_type_level_int len
-  let ty_id = mkVHDLExtId $ "vector_" ++ (show len_int)
-  -- TODO: Use el_ty
-  let range = AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len_int - 1))]
-  let ty_def = AST.TDA $ AST.ConsArrayDef range std_logic_ty
-  let ty_dec = AST.TypeDec ty_id ty_def
-  -- TODO: Check name uniqueness
-  State.modify (Map.insert (OrdType ty) (ty_id, ty_dec))
-  return ty_id
-
 -- | Create a VHDL vector type
 mk_vector_ty ::
   Int -- ^ The length of the vector