Don't generate ports for non-port signals.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 9cced3444d452607e3b8d35cc9b3ce631b6ee515..f875dd6b3ad5bee7876fcd624104940ab1937101 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -209,7 +209,7 @@ data BuiltIn = BuiltIn String [PortMap] PortMap
 -- | Map a port specification of a builtin function to a VHDL Signal to put in
 --   a VHDLSignalMap
 toVHDLSignalMap :: HsValueMap (String, AST.TypeMark) -> VHDLSignalMap
-toVHDLSignalMap = fmap (\(name, ty) -> (VHDL.mkVHDLId name, ty))
+toVHDLSignalMap = fmap (\(name, ty) -> Just (VHDL.mkVHDLId name, ty))
 
 -- | Translate a concise representation of a builtin function to something
 --   that can be put into FuncMap directly.