--core <- GHC.compileToCoreSimplified "Adders.hs"
core <- GHC.compileToCoreSimplified "Adders.hs"
--liftIO $ printBinds (cm_binds core)
- let binds = Maybe.mapMaybe (findBind (cm_binds core)) ["dff"]
+ let binds = Maybe.mapMaybe (findBind (cm_binds core)) ["sfull_adder"]
liftIO $ putStr $ prettyShow binds
-- Turn bind into VHDL
let (vhdl, sess) = State.runState (mkVHDL binds) (VHDLSession core 0 Map.empty)
modFuncs nameFlatFunction
modFuncs VHDL.createEntity
modFuncs VHDL.createArchitecture
- -- Extract the library units generated from all the functions in the
- -- session.
- funcs <- getFuncs
- let units = concat $ map VHDL.getLibraryUnits funcs
- return $ AST.DesignFile
- []
- units
+ VHDL.getDesignFile
findBind :: [CoreBind] -> String -> Maybe CoreBind
findBind binds lookfor =
let flatfunc = flattenFunction hsfunc bind
addFunc hsfunc
setFlatFunc hsfunc flatfunc
- let used_hsfuncs = map appFunc (flat_apps flatfunc)
+ let used_hsfuncs = Maybe.mapMaybe usedHsFunc (flat_defs flatfunc)
State.mapM resolvFunc used_hsfuncs
return ()
-- | Map a port specification of a builtin function to a VHDL Signal to put in
-- a VHDLSignalMap
toVHDLSignalMap :: HsValueMap (String, AST.TypeMark) -> VHDLSignalMap
-toVHDLSignalMap = fmap (\(name, ty) -> (VHDL.mkVHDLId name, ty))
+toVHDLSignalMap = fmap (\(name, ty) -> Just (VHDL.mkVHDLId name, ty))
-- | Translate a concise representation of a builtin function to something
-- that can be put into FuncMap directly.