Make the Alu example use 4-bit SizedWord as data.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 1ecbdb9223b3c4267649f4705e1ffa000b358de0..c4bcdbdf02084e9ad8ee8d1c2faf320873e983eb 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -8,6 +8,9 @@ import qualified Var
 import qualified Type
 import qualified TyCon
 import qualified DataCon
+import qualified HscMain
+import qualified SrcLoc
+import qualified FastString
 import qualified Maybe
 import qualified Module
 import qualified Data.Foldable as Foldable
@@ -46,7 +49,7 @@ import VHDLTypes
 import qualified VHDL
 
 main = do
-  makeVHDL "Alu.hs" "register_bank" True
+  makeVHDL "Alu.hs" "exec" True
 
 makeVHDL :: String -> String -> Bool -> IO ()
 makeVHDL filename name stateful = do
@@ -63,12 +66,17 @@ makeVHDL filename name stateful = do
 listBind :: String -> String -> IO ()
 listBind filename name = do
   core <- loadModule filename
-  let binds = findBinds core [name]
+  let [bind] = findBinds core [name]
   putStr "\n"
-  putStr $ prettyShow binds
+  putStr $ prettyShow bind
   putStr "\n\n"
-  putStr $ showSDoc $ ppr binds
+  putStr $ showSDoc $ ppr bind
   putStr "\n\n"
+  case bind of
+    NonRec b expr -> do 
+      putStr $ showSDoc $ ppr $ CoreUtils.exprType expr
+      putStr "\n\n"
+    otherwise -> return ()
 
 -- | Translate the binds with the given names from the given core module to
 --   VHDL. The Bool in the tuple makes the function stateful (True) or
@@ -268,9 +276,10 @@ resolvFunc ::
 
 resolvFunc hsfunc = do
   flatfuncmap <- getA tsFlatFuncs
-  -- Don't do anything if there is already a flat function for this hsfunc.
+  -- Don't do anything if there is already a flat function for this hsfunc or
+  -- when it is a builtin function.
   Monad.unless (Map.member hsfunc flatfuncmap) $ do
-  -- TODO: Builtin functions
+  Monad.unless (elem hsfunc VHDL.builtin_hsfuncs) $ do
   -- New function, resolve it
   core <- getA tsCoreModule
   -- Find the named function
@@ -352,33 +361,4 @@ splitTupleType ty =
         Nothing
     Nothing -> Nothing
 
--- | A consise representation of a (set of) ports on a builtin function
-type PortMap = HsValueMap (String, AST.TypeMark)
--- | A consise representation of a builtin function
-data BuiltIn = BuiltIn String [PortMap] PortMap
-
--- | Map a port specification of a builtin function to a VHDL Signal to put in
---   a VHDLSignalMap
-toVHDLSignalMap :: HsValueMap (String, AST.TypeMark) -> VHDLSignalMap
-toVHDLSignalMap = fmap (\(name, ty) -> Just (VHDL.mkVHDLId name, ty))
-
--- | Translate a concise representation of a builtin function to something
---   that can be put into FuncMap directly.
-{-
-addBuiltIn :: BuiltIn -> TranslatorState ()
-addBuiltIn (BuiltIn name args res) = do
-    addFunc hsfunc
-    setEntity hsfunc entity
-  where
-    hsfunc = HsFunction name (map useAsPort args) (useAsPort res)
-    entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing Nothing
-
-builtin_funcs = 
-  [ 
-    BuiltIn "hwxor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)),
-    BuiltIn "hwand" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)),
-    BuiltIn "hwor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)),
-    BuiltIn "hwnot" [(Single ("a", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty))
-  ]
--}
 -- vim: set ts=8 sw=2 sts=2 expandtab: