Create state procs for state signals.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 15349f1bf5e6bf2d3837fe4c5f1d91e8022a3a9a..c037a1e24a0d30a8f97aeca69c815fa65ad9e97d 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -33,8 +33,11 @@ import qualified ForSyDe.Backend.Ppr
 import Text.PrettyPrint.HughesPJ (render)
 
 import TranslatorTypes
+import HsValueMap
 import Pretty
 import Flatten
+import FlattenTypes
+import VHDLTypes
 import qualified VHDL
 
 main = 
@@ -51,7 +54,7 @@ main =
           --core <- GHC.compileToCoreSimplified "Adders.hs"
           core <- GHC.compileToCoreSimplified "Adders.hs"
           --liftIO $ printBinds (cm_binds core)
-          let binds = Maybe.mapMaybe (findBind (cm_binds core)) ["sfull_adder"]
+          let binds = Maybe.mapMaybe (findBind (cm_binds core)) ["dff"]
           liftIO $ putStr $ prettyShow binds
           -- Turn bind into VHDL
           let (vhdl, sess) = State.runState (mkVHDL binds) (VHDLSession core 0 Map.empty)
@@ -66,9 +69,16 @@ main =
       mapM addBuiltIn builtin_funcs
       -- Create entities and architectures for them
       mapM processBind binds
+      modFuncs nameFlatFunction
+      modFuncs VHDL.createEntity
+      modFuncs VHDL.createArchitecture
+      -- Extract the library units generated from all the functions in the
+      -- session.
+      funcs <- getFuncs
+      let units = concat $ map VHDL.getLibraryUnits funcs
       return $ AST.DesignFile 
         []
-        []
+        units
 
 findBind :: [CoreBind] -> String -> Maybe CoreBind
 findBind binds lookfor =
@@ -107,7 +117,7 @@ flattenBind hsfunc bind@(NonRec var expr) = do
   let flatfunc = flattenFunction hsfunc bind
   addFunc hsfunc
   setFlatFunc hsfunc flatfunc
-  let used_hsfuncs = map appFunc (apps flatfunc)
+  let used_hsfuncs = map appFunc (flat_apps flatfunc)
   State.mapM resolvFunc used_hsfuncs
   return ()
 
@@ -164,6 +174,24 @@ mkHsFunction f ty =
           error $ "Input state type of function " ++ hsname ++ ": " ++ (showSDoc $ ppr state_ty) ++ " does not match output state type: " ++ (showSDoc $ ppr outstate_ty)
       otherwise                -> error $ "Return type of top-level function " ++ hsname ++ " must be a two-tuple containing a state and output ports."
 
+-- | Adds signal names to the given FlatFunction
+nameFlatFunction ::
+  HsFunction
+  -> FuncData
+  -> VHDLState ()
+
+nameFlatFunction hsfunc fdata =
+  let func = flatFunc fdata in
+  case func of
+    -- Skip (builtin) functions without a FlatFunction
+    Nothing -> do return ()
+    -- Name the signals in all other functions
+    Just flatfunc ->
+      let s = flat_sigs flatfunc in
+      let s' = map (\(id, (SignalInfo Nothing use ty)) -> (id, SignalInfo (Just $ "sig_" ++ (show id)) use ty)) s in
+      let flatfunc' = flatfunc { flat_sigs = s' } in
+      setFlatFunc hsfunc flatfunc'
+
 -- | Splits a tuple type into a list of element types, or Nothing if the type
 --   is not a tuple type.
 splitTupleType ::
@@ -184,17 +212,27 @@ type PortMap = HsValueMap (String, AST.TypeMark)
 -- | A consise representation of a builtin function
 data BuiltIn = BuiltIn String [PortMap] PortMap
 
+-- | Map a port specification of a builtin function to a VHDL Signal to put in
+--   a VHDLSignalMap
+toVHDLSignalMap :: HsValueMap (String, AST.TypeMark) -> VHDLSignalMap
+toVHDLSignalMap = fmap (\(name, ty) -> (VHDL.mkVHDLId name, ty))
+
 -- | Translate a concise representation of a builtin function to something
 --   that can be put into FuncMap directly.
 addBuiltIn :: BuiltIn -> VHDLState ()
 addBuiltIn (BuiltIn name args res) = do
     addFunc hsfunc
+    setEntity hsfunc entity
   where
     hsfunc = HsFunction name (map useAsPort args) (useAsPort res)
+    entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing
 
 builtin_funcs = 
   [ 
-    BuiltIn "hwxor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty))
+    BuiltIn "hwxor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)),
+    BuiltIn "hwand" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)),
+    BuiltIn "hwor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)),
+    BuiltIn "hwnot" [(Single ("a", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty))
   ]
 
 -- vim: set ts=8 sw=2 sts=2 expandtab: