Name signals in a function after flattening it.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 15349f1bf5e6bf2d3837fe4c5f1d91e8022a3a9a..bb5845b6febe4f5d90185249d9cfcb1ced265d5e 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -33,8 +33,10 @@ import qualified ForSyDe.Backend.Ppr
 import Text.PrettyPrint.HughesPJ (render)
 
 import TranslatorTypes
+import HsValueMap
 import Pretty
 import Flatten
+import FlattenTypes
 import qualified VHDL
 
 main = 
@@ -66,6 +68,7 @@ main =
       mapM addBuiltIn builtin_funcs
       -- Create entities and architectures for them
       mapM processBind binds
+      modFuncs nameFlatFunction
       return $ AST.DesignFile 
         []
         []
@@ -164,6 +167,24 @@ mkHsFunction f ty =
           error $ "Input state type of function " ++ hsname ++ ": " ++ (showSDoc $ ppr state_ty) ++ " does not match output state type: " ++ (showSDoc $ ppr outstate_ty)
       otherwise                -> error $ "Return type of top-level function " ++ hsname ++ " must be a two-tuple containing a state and output ports."
 
+-- | Adds signal names to the given FlatFunction
+nameFlatFunction ::
+  HsFunction
+  -> FuncData
+  -> FuncData
+
+nameFlatFunction hsfunc fdata =
+  let func = flatFunc fdata in
+  case func of
+    -- Skip (builtin) functions without a FlatFunction
+    Nothing -> fdata
+    -- Name the signals in all other functions
+    Just flatfunc ->
+      let s = sigs flatfunc in
+      let s' = map (\(Signal id Nothing) -> Signal id (Just $ "sig_" ++ (show id))) s in
+      let flatfunc' = flatfunc { sigs = s' } in
+      fdata { flatFunc = Just flatfunc' }
+
 -- | Splits a tuple type into a list of element types, or Nothing if the type
 --   is not a tuple type.
 splitTupleType ::
@@ -194,7 +215,10 @@ addBuiltIn (BuiltIn name args res) = do
 
 builtin_funcs = 
   [ 
-    BuiltIn "hwxor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty))
+    BuiltIn "hwxor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)),
+    BuiltIn "hwand" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)),
+    BuiltIn "hwor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)),
+    BuiltIn "hwnot" [(Single ("a", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty))
   ]
 
 -- vim: set ts=8 sw=2 sts=2 expandtab: