Add the VHDLTypes module

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index bb5845b6febe4f5d90185249d9cfcb1ced265d5e..b7d3e0ef32d681fc2f80562212a79d7960611a54 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -69,9 +69,14 @@ main =
       -- Create entities and architectures for them
       mapM processBind binds
       modFuncs nameFlatFunction
+      modFuncs VHDL.createEntity
+      -- Extract the library units generated from all the functions in the
+      -- session.
+      funcs <- getFuncs
+      let units = concat $ map VHDL.getLibraryUnits funcs
       return $ AST.DesignFile 
         []
-        []
+        units
 
 findBind :: [CoreBind] -> String -> Maybe CoreBind
 findBind binds lookfor =
@@ -181,7 +186,7 @@ nameFlatFunction hsfunc fdata =
     -- Name the signals in all other functions
     Just flatfunc ->
       let s = sigs flatfunc in
-      let s' = map (\(Signal id Nothing) -> Signal id (Just $ "sig_" ++ (show id))) s in
+      let s' = map (\(id, (SignalInfo Nothing)) -> (id, SignalInfo (Just $ "sig_" ++ (show id)))) s in
       let flatfunc' = flatfunc { sigs = s' } in
       fdata { flatFunc = Just flatfunc' }