Add the VHDLTypes module

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 6b96ebca98a04566fb07e0adaeec609fc94a5d77..b7d3e0ef32d681fc2f80562212a79d7960611a54 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -69,9 +69,14 @@ main =
       -- Create entities and architectures for them
       mapM processBind binds
       modFuncs nameFlatFunction
+      modFuncs VHDL.createEntity
+      -- Extract the library units generated from all the functions in the
+      -- session.
+      funcs <- getFuncs
+      let units = concat $ map VHDL.getLibraryUnits funcs
       return $ AST.DesignFile 
         []
-        []
+        units
 
 findBind :: [CoreBind] -> String -> Maybe CoreBind
 findBind binds lookfor =