import Pretty
import Flatten
import FlattenTypes
+import VHDLTypes
import qualified VHDL
main =
--core <- GHC.compileToCoreSimplified "Adders.hs"
core <- GHC.compileToCoreSimplified "Adders.hs"
--liftIO $ printBinds (cm_binds core)
- let binds = Maybe.mapMaybe (findBind (cm_binds core)) ["sfull_adder"]
+ let binds = Maybe.mapMaybe (findBind (cm_binds core)) ["dff"]
liftIO $ putStr $ prettyShow binds
-- Turn bind into VHDL
let (vhdl, sess) = State.runState (mkVHDL binds) (VHDLSession core 0 Map.empty)
mapM addBuiltIn builtin_funcs
-- Create entities and architectures for them
mapM processBind binds
- return $ AST.DesignFile
- []
- []
+ modFuncs nameFlatFunction
+ modFuncs VHDL.createEntity
+ modFuncs VHDL.createArchitecture
+ VHDL.getDesignFile
findBind :: [CoreBind] -> String -> Maybe CoreBind
findBind binds lookfor =
let flatfunc = flattenFunction hsfunc bind
addFunc hsfunc
setFlatFunc hsfunc flatfunc
- let used_hsfuncs = map appFunc (apps flatfunc)
+ let used_hsfuncs = map appFunc (flat_apps flatfunc)
State.mapM resolvFunc used_hsfuncs
return ()
error $ "Input state type of function " ++ hsname ++ ": " ++ (showSDoc $ ppr state_ty) ++ " does not match output state type: " ++ (showSDoc $ ppr outstate_ty)
otherwise -> error $ "Return type of top-level function " ++ hsname ++ " must be a two-tuple containing a state and output ports."
+-- | Adds signal names to the given FlatFunction
+nameFlatFunction ::
+ HsFunction
+ -> FuncData
+ -> VHDLState ()
+
+nameFlatFunction hsfunc fdata =
+ let func = flatFunc fdata in
+ case func of
+ -- Skip (builtin) functions without a FlatFunction
+ Nothing -> do return ()
+ -- Name the signals in all other functions
+ Just flatfunc ->
+ let s = flat_sigs flatfunc in
+ let s' = map (\(id, (SignalInfo Nothing use ty)) -> (id, SignalInfo (Just $ "sig_" ++ (show id)) use ty)) s in
+ let flatfunc' = flatfunc { flat_sigs = s' } in
+ setFlatFunc hsfunc flatfunc'
+
-- | Splits a tuple type into a list of element types, or Nothing if the type
-- is not a tuple type.
splitTupleType ::
-- | A consise representation of a builtin function
data BuiltIn = BuiltIn String [PortMap] PortMap
+-- | Map a port specification of a builtin function to a VHDL Signal to put in
+-- a VHDLSignalMap
+toVHDLSignalMap :: HsValueMap (String, AST.TypeMark) -> VHDLSignalMap
+toVHDLSignalMap = fmap (\(name, ty) -> (VHDL.mkVHDLId name, ty))
+
-- | Translate a concise representation of a builtin function to something
-- that can be put into FuncMap directly.
addBuiltIn :: BuiltIn -> VHDLState ()
addBuiltIn (BuiltIn name args res) = do
addFunc hsfunc
+ setEntity hsfunc entity
where
hsfunc = HsFunction name (map useAsPort args) (useAsPort res)
+ entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing
builtin_funcs =
[