Mark all signals as ports or states when appropriate.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 9ce7206c9df9bd841bd0c5a4e7cccabe1d392b3f..9cced3444d452607e3b8d35cc9b3ce631b6ee515 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -54,7 +54,7 @@ main =
           --core <- GHC.compileToCoreSimplified "Adders.hs"
           core <- GHC.compileToCoreSimplified "Adders.hs"
           --liftIO $ printBinds (cm_binds core)
-          let binds = Maybe.mapMaybe (findBind (cm_binds core)) ["sfull_adder"]
+          let binds = Maybe.mapMaybe (findBind (cm_binds core)) ["dff"]
           liftIO $ putStr $ prettyShow binds
           -- Turn bind into VHDL
           let (vhdl, sess) = State.runState (mkVHDL binds) (VHDLSession core 0 Map.empty)
@@ -72,13 +72,7 @@ main =
       modFuncs nameFlatFunction
       modFuncs VHDL.createEntity
       modFuncs VHDL.createArchitecture
-      -- Extract the library units generated from all the functions in the
-      -- session.
-      funcs <- getFuncs
-      let units = concat $ map VHDL.getLibraryUnits funcs
-      return $ AST.DesignFile 
-        []
-        units
+      VHDL.getDesignFile
 
 findBind :: [CoreBind] -> String -> Maybe CoreBind
 findBind binds lookfor =