Add another higher order testcase, highordtest2.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 32d2addfee4b79afe25822b2fe0f2c486c3d9929..7b548e7c8d67bb63da79dffe3bfa6dbe91ed814d 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -53,7 +53,7 @@ import VHDLTypes
 import qualified VHDL
 
 main = do
-  makeVHDL "Alu.hs" "exec" True
+  makeVHDL "Adders.hs" "highordtest2" True
 
 makeVHDL :: String -> String -> Bool -> IO ()
 makeVHDL filename name stateful = do