Adders.hs explicityly uses Prelude lists function. TFVec function are the default

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 32d2addfee4b79afe25822b2fe0f2c486c3d9929..6b0cdd1e06c298e4a8261cb707274e1e9bd3ab7d 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -52,9 +52,6 @@ import FlattenTypes
 import VHDLTypes
 import qualified VHDL
 
-main = do
-  makeVHDL "Alu.hs" "exec" True
-
 makeVHDL :: String -> String -> Bool -> IO ()
 makeVHDL filename name stateful = do
   -- Load the module
@@ -62,7 +59,7 @@ makeVHDL filename name stateful = do
   -- Translate to VHDL
   vhdl <- moduleToVHDL core [(name, stateful)]
   -- Write VHDL to file
-  let dir = "../vhdl/vhdl/" ++ name ++ "/"
+  let dir = "./vhdl/" ++ name ++ "/"
   mapM (writeVHDL dir) vhdl
   return ()