Adders.hs explicityly uses Prelude lists function. TFVec function are the default

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 0f60277671f99b646ec427deb8fd82ce92d53169..6b0cdd1e06c298e4a8261cb707274e1e9bd3ab7d 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -52,9 +52,6 @@ import FlattenTypes
 import VHDLTypes
 import qualified VHDL
 
--- main = do
---   makeVHDL "Alu.hs" "exec" True
-
 makeVHDL :: String -> String -> Bool -> IO ()
 makeVHDL filename name stateful = do
   -- Load the module