-- Create entities and architectures for them
Monad.zipWithM processBind statefuls binds
modFuncs nameFlatFunction
- modFuncs VHDL.createEntity
+ modFuncMap $ Map.mapWithKey (\hsfunc fdata -> fdata {funcEntity = VHDL.createEntity hsfunc fdata})
modFuncs VHDL.createArchitecture
- VHDL.getDesignFiles
+ funcs <- getFuncs
+ return $ VHDL.getDesignFiles (map snd funcs)
-- | Write the given design file to a file inside the given dir
-- The first library unit in the designfile must be an entity, whose name
setEntity hsfunc entity
where
hsfunc = HsFunction name (map useAsPort args) (useAsPort res)
- entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing
+ entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing Nothing
builtin_funcs =
[