Add a getFuncMap accessor for VHDLState.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 383c477282e04fa3429c153520cf13064eca1d0d..6a784251d3c310240fc657b8a0c183980cc80202 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -92,9 +92,10 @@ moduleToVHDL core list = do
       -- Create entities and architectures for them
       Monad.zipWithM processBind statefuls binds
       modFuncs nameFlatFunction
-      modFuncs VHDL.createEntity
+      modFuncMap $ Map.mapWithKey (\hsfunc fdata -> fdata {funcEntity = VHDL.createEntity hsfunc fdata})
       modFuncs VHDL.createArchitecture
-      VHDL.getDesignFiles
+      funcs <- getFuncs
+      return $ VHDL.getDesignFiles (map snd funcs)
 
 -- | Write the given design file to a file inside the given dir
 --   The first library unit in the designfile must be an entity, whose name