-- ForSyDe to get access to these modules.
import qualified ForSyDe.Backend.VHDL.AST as AST
import qualified ForSyDe.Backend.VHDL.Ppr
+import qualified ForSyDe.Backend.VHDL.FileIO
import qualified ForSyDe.Backend.Ppr
-- This is needed for rendering the pretty printed VHDL
import Text.PrettyPrint.HughesPJ (render)
-- Turn bind into VHDL
let vhdl = State.evalState (mkVHDL binds) (VHDLSession 0 [])
liftIO $ putStr $ render $ ForSyDe.Backend.Ppr.ppr vhdl
+ liftIO $ ForSyDe.Backend.VHDL.FileIO.writeDesignFile vhdl "../vhdl/vhdl/output.vhdl"
return ()
where
-- Turns the given bind into VHDL
mkVHDL binds = do
-- Add the builtin functions
mapM (uncurry addFunc) builtin_funcs
- -- Get the function signatures
- funcs <- mapM mkHWFunction binds
- -- Add them to the session
- mapM (uncurry addFunc) funcs
- let entities = map getEntity (snd $ unzip funcs)
- -- Create architectures for them
- archs <- mapM getArchitecture binds
+ -- Create entities and architectures for them
+ units <- mapM expandBind binds
return $ AST.DesignFile
[]
- ((map AST.LUEntity entities) ++ (map AST.LUArch archs))
+ (concat units)
printTarget (Target (TargetFile file (Just x)) obj Nothing) =
print $ show file
-- Accepts a port name and an argument to map to it.
-- Returns the appropriate line for in the port map
-getPortMapEntry (Signal portname) (Signal signame) =
+getPortMapEntry (Single (portname, _)) (Single (signame, _)) =
(Just portname) AST.:=>: (AST.ADName (AST.NSimple signame))
-
-getInstantiations ::
- [SignalNameMap] -- The arguments that need to be applied to the
- -- expression.
- -> SignalNameMap -- The output ports that the expression should generate.
- -> [(CoreBndr, SignalNameMap)]
- -- A list of bindings in effect
- -> CoreSyn.CoreExpr -- The expression to generate an architecture for
- -> VHDLState ([AST.SigDec], [AST.ConcSm])
- -- The resulting VHDL code
-
--- A lambda expression binds the first argument (a) to the binder b.
-getInstantiations (a:as) outs binds (Lam b expr) =
- getInstantiations as outs ((b, a):binds) expr
-
--- A case expression that checks a single variable and has a single
--- alternative, can be used to take tuples apart
-getInstantiations args outs binds (Case (Var v) b _ [res]) =
- -- Split out the type of alternative constructor, the variables it binds
- -- and the expression to evaluate with the variables bound.
- let (altcon, bind_vars, expr) = res in
- case altcon of
- DataAlt datacon ->
- if (DataCon.isTupleCon datacon) then
- let
- -- Lookup the scrutinee (which must be a variable bound to a tuple) in
- -- the existing bindings list and get the portname map for each of
- -- it's elements.
- Tuple tuple_ports = Maybe.fromMaybe
- (error $ "Case expression uses unknown scrutinee " ++ getOccString v)
- (lookup v binds)
- -- Merge our existing binds with the new binds.
- binds' = (zip bind_vars tuple_ports) ++ binds
- in
- -- Evaluate the expression with the new binds list
- getInstantiations args outs binds' expr
- else
- error "Data constructors other than tuples not supported"
- otherwise ->
- error "Case binders other than tuples not supported"
-
--- An application is an instantiation of a component
-getInstantiations args outs binds app@(App expr arg) = do
- let ((Var f), fargs) = collectArgs app
- name = getOccString f
- if isTupleConstructor f
- then do
- -- Get the signals we should bind our results to
- let Tuple outports = outs
- -- Split the tuple constructor arguments into types and actual values.
- let (_, vals) = splitTupleConstructorArgs fargs
- -- Bind each argument to each output signal
- res <- sequence $ zipWith
- (\outs' expr' -> getInstantiations args outs' binds expr')
- outports vals
- -- res is a list of pairs of lists, so split out the signals and
- -- components into separate lists of lists
- let (sigs, comps) = unzip res
- -- And join all the signals and component instantiations together
- return $ (concat sigs, concat comps)
- else do
- -- This is an normal function application, which maps to a component
- -- instantiation.
- -- Lookup the hwfunction to instantiate
- HWFunction vhdl_id inports outport <- getHWFunc name
- -- Generate a unique name for the application
- appname <- uniqueName "app"
- -- Expand each argument to a signal or port name, possibly generating
- -- new signals and component instantiations
- (sigs, comps, args) <- expandArgs binds fargs
- -- Bind each of the input ports to the expanded signal or port
- let inmaps = zipWith getPortMapEntry inports args
- -- Bind each of the output ports to our output signals
- let outmaps = mapOutputPorts outport outs
- -- Build and return a component instantiation
- let comp = AST.CompInsSm
- (AST.unsafeVHDLBasicId appname)
- (AST.IUEntity (AST.NSimple vhdl_id))
- (AST.PMapAspect (inmaps ++ outmaps))
- return (sigs, (AST.CSISm comp) : comps)
-
-getInstantiations args outs binds expr =
- error $ "Unsupported expression" ++ (showSDoc $ ppr $ expr)
-
expandExpr ::
[(CoreBndr, SignalNameMap)]
-- A list of bindings in effect
-- the expression's result.
expandExpr binds lam@(Lam b expr) = do
-- Generate a new signal to which we will expect this argument to be bound.
- signal_name <- uniqueName ("arg-" ++ getOccString b)
+ signal_name <- uniqueName ("arg_" ++ getOccString b)
-- Find the type of the binder
let (arg_ty, _) = Type.splitFunTy (CoreUtils.exprType lam)
-- Create signal names for the binder
res_signal')
expandExpr binds (Var id) =
- return ([], [], [], Signal signal_id)
+ return ([], [], [], Single (signal_id, ty))
where
-- Lookup the id in our binds map
- Signal signal_id = Maybe.fromMaybe
+ Single (signal_id, ty) = Maybe.fromMaybe
(error $ "Argument " ++ getOccString id ++ "is unknown")
(lookup id binds)
res_signals')
expandExpr binds app@(App _ _) = do
- let ((Var f), args) = collectArgs app
- if isTupleConstructor f
- then
- expandBuildTupleExpr binds args
- else
+ -- Is this a data constructor application?
+ case CoreUtils.exprIsConApp_maybe app of
+ -- Is this a tuple construction?
+ Just (dc, args) -> if DataCon.isTupleCon dc
+ then
+ expandBuildTupleExpr binds (dataConAppArgs dc args)
+ else
+ error "Data constructors other than tuples not supported"
+ otherise ->
+ -- Normal function application, should map to a component instantiation
+ let ((Var f), args) = collectArgs app in
expandApplicationExpr binds (CoreUtils.exprType app) f args
expandExpr binds expr@(Case (Var v) b _ alts) =
-- See expandExpr
expandBuildTupleExpr binds args = do
-- Split the tuple constructor arguments into types and actual values.
- let (_, vals) = splitTupleConstructorArgs args
-- Expand each of the values in the tuple
(signals_declss, statementss, arg_signalss, res_signals) <-
- (Monad.liftM List.unzip4) $ mapM (expandExpr binds) vals
+ (Monad.liftM List.unzip4) $ mapM (expandExpr binds) args
if any (not . null) arg_signalss
then error "Putting high order functions in tuples not supported"
else
expandApplicationExpr binds ty f args = do
let name = getOccString f
-- Generate a unique name for the application
- appname <- uniqueName ("app-" ++ name)
+ appname <- uniqueName ("app_" ++ name)
-- Lookup the hwfunction to instantiate
- HWFunction vhdl_id inports outport <- getHWFunc name
+ HWFunction vhdl_id inports outport <- getHWFunc (appToHsFunction f args ty)
-- Expand each of the args, so each of them is reduced to output signals
(arg_signal_decls, arg_statements, arg_res_signals) <- expandArgs binds args
-- Bind each of the input ports to the expanded arguments
let inmaps = concat $ zipWith createAssocElems inports arg_res_signals
-- Create signal names for our result
- let res_signal = getPortNameMapForTy (appname ++ "-out") ty
+ let res_signal = getPortNameMapForTy (appname ++ "_out") ty
-- Create the corresponding signal declarations
let signal_decls = mkSignalsFromMap res_signal
-- Bind each of the output ports to our output signals
-> SignalNameMap -- The signals to bind to it
-> [AST.AssocElem] -- The resulting port map lines
-createAssocElems (Signal port_id) (Signal signal_id) =
+createAssocElems (Single (port_id, _)) (Single (signal_id, _)) =
[(Just port_id) AST.:=>: (AST.ADName (AST.NSimple signal_id))]
createAssocElems (Tuple ports) (Tuple signals) =
SignalNameMap
-> [AST.SigDec]
-mkSignalsFromMap (Signal id) =
- -- TODO: This uses the bit type hardcoded
- [mkSignalFromId id vhdl_bit_ty]
+mkSignalsFromMap (Single (id, ty)) =
+ [mkSignalFromId id ty]
mkSignalsFromMap (Tuple signals) =
concat $ map mkSignalsFromMap signals
expandArgs _ [] = return ([], [], [])
--- Is the given name a (binary) tuple constructor
-isTupleConstructor :: Var.Var -> Bool
-isTupleConstructor var =
- Name.isWiredInName name
- && Name.nameModule name == tuple_mod
- && (Name.occNameString $ Name.nameOccName name) == "(,)"
+-- Extract the arguments from a data constructor application (that is, the
+-- normal args, leaving out the type args).
+dataConAppArgs :: DataCon -> [CoreExpr] -> [CoreExpr]
+dataConAppArgs dc args =
+ drop tycount args
where
- name = Var.varName var
- mod = nameModule name
- tuple_mod = Module.mkModule (Module.stringToPackageId "ghc-prim") (Module.mkModuleName "GHC.Tuple")
-
--- Split arguments into type arguments and value arguments This is probably
--- not really sufficient (not sure if Types can actually occur as value
--- arguments...)
-splitTupleConstructorArgs :: [CoreExpr] -> ([CoreExpr], [CoreExpr])
-splitTupleConstructorArgs (e:es) =
- case e of
- Type t -> (e:tys, vals)
- otherwise -> (tys, e:vals)
- where
- (tys, vals) = splitTupleConstructorArgs es
-
-splitTupleConstructorArgs [] = ([], [])
+ tycount = length $ DataCon.dataConAllTyVars dc
mapOutputPorts ::
SignalNameMap -- The output portnames of the component
-- Map the output port of a component to the output port of the containing
-- entity.
-mapOutputPorts (Signal portname) (Signal signalname) =
+mapOutputPorts (Single (portname, _)) (Single (signalname, _)) =
[(Just portname) AST.:=>: (AST.ADName (AST.NSimple signalname))]
-- Map matching output ports in the tuple
mapOutputPorts (Tuple ports) (Tuple signals) =
concat (zipWith mapOutputPorts ports signals)
+expandBind ::
+ CoreBind -- The binder to expand into VHDL
+ -> VHDLState [AST.LibraryUnit] -- The resulting VHDL
+
+expandBind (Rec _) = error "Recursive binders not supported"
+
+expandBind bind@(NonRec var expr) = do
+ -- Create the function signature
+ hwfunc <- mkHWFunction bind
+ let ty = CoreUtils.exprType expr
+ let hsfunc = mkHsFunction var ty
+ -- Add it to the session
+ addFunc hsfunc hwfunc
+ arch <- getArchitecture hwfunc expr
+ let entity = getEntity hwfunc
+ return $ [
+ AST.LUEntity entity,
+ AST.LUArch arch ]
+
getArchitecture ::
- CoreBind -- The binder to expand into an architecture
+ HWFunction -- The function to generate an architecture for
+ -> CoreExpr -- The expression that is bound to the function
-> VHDLState AST.ArchBody -- The resulting architecture
-getArchitecture (Rec _) = error "Recursive binders not supported"
-
-getArchitecture (NonRec var expr) = do
- let name = (getOccString var)
- HWFunction vhdl_id inports outport <- getHWFunc name
- sess <- State.get
+getArchitecture hwfunc expr = do
+ -- Unpack our hwfunc
+ let HWFunction vhdl_id inports outport = hwfunc
+ -- Expand the expression into an architecture body
(signal_decls, statements, arg_signals, res_signal) <- expandExpr [] expr
let inport_assigns = concat $ zipWith createSignalAssignments arg_signals inports
let outport_assigns = createSignalAssignments outport res_signal
-> SignalNameMap -- The ports to generate a map for
-> [AST.IfaceSigDec] -- The resulting ports
-mkIfaceSigDecs mode (Signal port_id) =
- -- TODO: Remove hardcoded type
- [AST.IfaceSigDec port_id mode vhdl_bit_ty]
+mkIfaceSigDecs mode (Single (port_id, ty)) =
+ [AST.IfaceSigDec port_id mode ty]
mkIfaceSigDecs mode (Tuple ports) =
concat $ map (mkIfaceSigDecs mode) ports
-- A simple assignment of one signal to another (greatly complicated because
-- signal assignments can be conditional with multiple conditions in VHDL).
-createSignalAssignments (Signal dst) (Signal src) =
+createSignalAssignments (Single (dst, _)) (Single (src, _)) =
[AST.CSSASm assign]
where
src_name = AST.NSimple src
createSignalAssignments dst src =
error $ "Non matching source and destination: " ++ show dst ++ "\nand\n" ++ show src
-data SignalNameMap =
- Tuple [SignalNameMap]
- | Signal AST.VHDLId
- deriving (Show)
+type SignalNameMap = HsValueMap (AST.VHDLId, AST.TypeMark)
+
+-- | A datatype that maps each of the single values in a haskell structure to
+-- a mapto. The map has the same structure as the haskell type mapped, ie
+-- nested tuples etc.
+data HsValueMap mapto =
+ Tuple [HsValueMap mapto]
+ | Single mapto
+ deriving (Show, Eq)
+
+-- | Creates a HsValueMap with the same structure as the given type, using the
+-- given function for mapping the single types.
+mkHsValueMap ::
+ (Type -> HsValueMap mapto) -- ^ A function to map single value Types
+ -- (basically anything but tuples) to a
+ -- HsValueMap (not limited to the Single
+ -- constructor)
+ -> Type -- ^ The type to map to a HsValueMap
+ -> HsValueMap mapto -- ^ The resulting map
+
+mkHsValueMap f ty =
+ case Type.splitTyConApp_maybe ty of
+ Just (tycon, args) ->
+ if (TyCon.isTupleTyCon tycon)
+ then
+ -- Handle tuple construction especially
+ Tuple (map (mkHsValueMap f) args)
+ else
+ -- And let f handle the rest
+ f ty
+ -- And let f handle the rest
+ Nothing -> f ty
-- Generate a port name map (or multiple for tuple types) in the given direction for
-- each type given.
-- Expand tuples we find
Tuple (getPortNameMapForTys name 0 args)
else -- Assume it's a type constructor application, ie simple data type
- -- TODO: Add type?
- Signal (AST.unsafeVHDLBasicId name)
+ Single ((AST.unsafeVHDLBasicId name), (vhdl_ty ty))
where
(tycon, args) = Type.splitTyConApp ty
-- output ports.
mkHWFunction ::
CoreBind -- The core binder to generate the interface for
- -> VHDLState (String, HWFunction) -- The name of the function and its interface
+ -> VHDLState HWFunction -- The function interface
mkHWFunction (NonRec var expr) =
- return (name, HWFunction (mkVHDLId name) inports outport)
+ return $ HWFunction (mkVHDLId name) inports outport
where
name = getOccString var
ty = CoreUtils.exprType expr
mkHWFunction (Rec _) =
error "Recursive binders not supported"
+-- | How is a given (single) value in a function's type (ie, argument or
+-- return value) used?
+data HsValueUse =
+ Port -- ^ Use it as a port (input or output)
+ deriving (Show, Eq)
+
+-- | This type describes a particular use of a Haskell function and is used to
+-- look up an appropriate hardware description.
+data HsFunction = HsFunction {
+ hsName :: String, -- ^ What was the name of the original Haskell function?
+ hsArgs :: [HsValueMap HsValueUse], -- ^ How are the arguments used?
+ hsRes :: HsValueMap HsValueUse -- ^ How is the result value used?
+} deriving (Show, Eq)
+
+-- | Translate a function application to a HsFunction. i.e., which function
+-- do you need to translate this function application.
+appToHsFunction ::
+ Var.Var -- ^ The function to call
+ -> [CoreExpr] -- ^ The function arguments
+ -> Type -- ^ The return type
+ -> HsFunction -- ^ The needed HsFunction
+
+appToHsFunction f args ty =
+ HsFunction hsname hsargs hsres
+ where
+ mkPort = \x -> Single Port
+ hsargs = map (mkHsValueMap mkPort . CoreUtils.exprType) args
+ hsres = mkHsValueMap mkPort ty
+ hsname = getOccString f
+
+-- | Translate a top level function declaration to a HsFunction. i.e., which
+-- interface will be provided by this function. This function essentially
+-- defines the "calling convention" for hardware models.
+mkHsFunction ::
+ Var.Var -- ^ The function defined
+ -> Type -- ^ The function type (including arguments!)
+ -> HsFunction -- ^ The resulting HsFunction
+
+mkHsFunction f ty =
+ HsFunction hsname hsargs hsres
+ where
+ (arg_tys, res_ty) = Type.splitFunTys ty
+ mkPort = \x -> Single Port
+ hsargs = map (mkHsValueMap mkPort) arg_tys
+ hsres = mkHsValueMap mkPort res_ty
+ hsname = getOccString f
+
data VHDLSession = VHDLSession {
- nameCount :: Int, -- A counter that can be used to generate unique names
- funcs :: [(String, HWFunction)] -- All functions available, indexed by name
+ nameCount :: Int, -- A counter that can be used to generate unique names
+ funcs :: [(HsFunction, HWFunction)] -- All functions available
} deriving (Show)
type VHDLState = State.State VHDLSession
-- Add the function to the session
-addFunc :: String -> HWFunction -> VHDLState ()
-addFunc name f = do
+addFunc :: HsFunction -> HWFunction -> VHDLState ()
+addFunc hsfunc hwfunc = do
fs <- State.gets funcs -- Get the funcs element from the session
- State.modify (\x -> x {funcs = (name, f) : fs }) -- Prepend name and f
+ State.modify (\x -> x {funcs = (hsfunc, hwfunc) : fs }) -- Prepend name and f
-- Lookup the function with the given name in the current session. Errors if
-- it was not found.
-getHWFunc :: String -> VHDLState HWFunction
-getHWFunc name = do
+getHWFunc :: HsFunction -> VHDLState HWFunction
+getHWFunc hsfunc = do
fs <- State.gets funcs -- Get the funcs element from the session
return $ Maybe.fromMaybe
- (error $ "Function " ++ name ++ "is unknown? This should not happen!")
- (lookup name fs)
+ (error $ "Function " ++ (hsName hsfunc) ++ "is unknown? This should not happen!")
+ (lookup hsfunc fs)
-- Makes the given name unique by appending a unique number.
-- This does not do any checking against existing names, so it only guarantees
uniqueName name = do
count <- State.gets nameCount -- Get the funcs element from the session
State.modify (\s -> s {nameCount = count + 1})
- return $ name ++ "-" ++ (show count)
+ return $ name ++ "_" ++ (show count)
-- Shortcut
mkVHDLId :: String -> AST.VHDLId
builtin_funcs =
[
- ("hwxor", HWFunction (mkVHDLId "hwxor") [Signal $ mkVHDLId "a", Signal $ mkVHDLId "b"] (Signal $ mkVHDLId "o")),
- ("hwand", HWFunction (mkVHDLId "hwand") [Signal $ mkVHDLId "a", Signal $ mkVHDLId "b"] (Signal $ mkVHDLId "o")),
- ("hwor", HWFunction (mkVHDLId "hwor") [Signal $ mkVHDLId "a", Signal $ mkVHDLId "b"] (Signal $ mkVHDLId "o")),
- ("hwnot", HWFunction (mkVHDLId "hwnot") [Signal $ mkVHDLId "i"] (Signal $ mkVHDLId "o"))
+ (HsFunction "hwxor" [(Single Port), (Single Port)] (Single Port), HWFunction (mkVHDLId "hwxor") [Single (mkVHDLId "a", vhdl_bit_ty), Single (mkVHDLId "b", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty))),
+ (HsFunction "hwand" [(Single Port), (Single Port)] (Single Port), HWFunction (mkVHDLId "hwand") [Single (mkVHDLId "a", vhdl_bit_ty), Single (mkVHDLId "b", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty))),
+ (HsFunction "hwor" [(Single Port), (Single Port)] (Single Port), HWFunction (mkVHDLId "hwor") [Single (mkVHDLId "a", vhdl_bit_ty), Single (mkVHDLId "b", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty))),
+ (HsFunction "hwnot" [(Single Port)] (Single Port), HWFunction (mkVHDLId "hwnot") [Single (mkVHDLId "i", vhdl_bit_ty)] (Single (mkVHDLId "o", vhdl_bit_ty)))
]
vhdl_bit_ty :: AST.TypeMark
vhdl_bit_ty = AST.unsafeVHDLBasicId "Bit"
+-- Translate a Haskell type to a VHDL type
+vhdl_ty :: Type -> AST.TypeMark
+vhdl_ty ty = Maybe.fromMaybe
+ (error $ "Unsupported Haskell type: " ++ (showSDoc $ ppr ty))
+ (vhdl_ty_maybe ty)
+
+-- Translate a Haskell type to a VHDL type
+vhdl_ty_maybe :: Type -> Maybe AST.TypeMark
+vhdl_ty_maybe ty =
+ case Type.splitTyConApp_maybe ty of
+ Just (tycon, args) ->
+ let name = TyCon.tyConName tycon in
+ -- TODO: Do something more robust than string matching
+ case getOccString name of
+ "Bit" -> Just vhdl_bit_ty
+ otherwise -> Nothing
+ otherwise -> Nothing
+
-- vim: set ts=8 sw=2 sts=2 expandtab:
projects / matthijs / master-project / cλash.git / blobdiff