Remove createArchitecture from the VHDLState Monad.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index c66db947dfecdf19b9859303d3bf2368aff7e03f..2a752a79d34c94cc5ccc4b32cc296b7aaeade5d2 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -93,7 +93,8 @@ moduleToVHDL core list = do
       Monad.zipWithM processBind statefuls binds
       modFuncMap $ Map.map (\fdata -> fdata {flatFunc = fmap nameFlatFunction (flatFunc fdata)})
       modFuncMap $ Map.mapWithKey (\hsfunc fdata -> fdata {funcEntity = VHDL.createEntity hsfunc fdata})
-      modFuncs VHDL.createArchitecture
+      funcs <- getFuncMap
+      modFuncMap $ Map.mapWithKey (\hsfunc fdata -> fdata {funcArch = VHDL.createArchitecture funcs hsfunc fdata})
       funcs <- getFuncs
       return $ VHDL.getDesignFiles (map snd funcs)