import qualified VHDL
main = do
+ makeVHDL "Alu.hs" "register_bank"
+
+makeVHDL :: String -> String -> IO ()
+makeVHDL filename name = do
-- Load the module
- core <- loadModule "Alu.hs"
+ core <- loadModule filename
-- Translate to VHDL
- vhdl <- moduleToVHDL core ["salu"]
+ vhdl <- moduleToVHDL core [name]
-- Write VHDL to file
writeVHDL vhdl "../vhdl/vhdl/output.vhdl"
let binds = findBinds core [name]
putStr "\n"
putStr $ prettyShow binds
+ putStr $ showSDoc $ ppr binds
putStr "\n\n"
-- | Translate the binds with the given names from the given core module to
-- Name the signals in all other functions
Just flatfunc ->
let s = flat_sigs flatfunc in
- let s' = map (\(id, (SignalInfo Nothing use ty)) -> (id, SignalInfo (Just $ "sig_" ++ (show id)) use ty)) s in
+ let s' = map (\(id, (SignalInfo Nothing use ty hints)) -> (id, SignalInfo (Just $ "sig_" ++ (show id)) use ty hints)) s in
let flatfunc' = flatfunc { flat_sigs = s' } in
setFlatFunc hsfunc flatfunc'