import qualified VHDL
main = do
- makeVHDL "Alu.hs" "salu"
+ makeVHDL "Alu.hs" "register_bank"
makeVHDL :: String -> String -> IO ()
makeVHDL filename name = do
let binds = findBinds core [name]
putStr "\n"
putStr $ prettyShow binds
+ putStr $ showSDoc $ ppr binds
putStr "\n\n"
-- | Translate the binds with the given names from the given core module to