Add a base case to splitTupleConstructorArgs.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index de091dc2f74c1e537b19e5fb4a131ffa045eeb02..12393e8891f175dec71bedf6e7266a998f534a5b 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -374,6 +374,8 @@ splitTupleConstructorArgs (e:es) =
   where
     (tys, vals) = splitTupleConstructorArgs es
 
+splitTupleConstructorArgs [] = ([], [])
+
 mapOutputPorts ::
   SignalNameMap AST.VHDLId      -- The output portnames of the component
   -> SignalNameMap AST.VHDLId   -- The output portnames and/or signals to map these to