Add a Type to a Literal SignalExpr.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 396dfbc40e8e03769fea16d673281a0baeb01865..071e9d296dc5f416b6da9d1bfc2ed93a00e07742 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -49,7 +49,7 @@ import VHDLTypes
 import qualified VHDL
 
 main = do
-  makeVHDL "Alu.hs" "register_bank" True
+  makeVHDL "Alu.hs" "exec" True
 
 makeVHDL :: String -> String -> Bool -> IO ()
 makeVHDL filename name stateful = do
@@ -176,7 +176,7 @@ flattenBind hsfunc bind@(NonRec var expr) = do
   -- Propagate state variables
   let flatfunc' = propagateState hsfunc flatfunc
   -- Store the flat function in the session
-  modA tsFlatFuncs (Map.insert hsfunc flatfunc)
+  modA tsFlatFuncs (Map.insert hsfunc flatfunc')
   -- Flatten any functions used
   let used_hsfuncs = Maybe.mapMaybe usedHsFunc (flat_defs flatfunc')
   mapM_ resolvFunc used_hsfuncs