Remove createArchitecture from the VHDLState Monad.

[matthijs/master-project/cλash.git] / Pretty.hs

diff --git a/Pretty.hs b/Pretty.hs
index 7c9840450339be35f57184f950824042fcc41283..eb8378c6c1e1f03e640ac9ec575c5d89229851b0 100644 (file)
--- a/Pretty.hs
+++ b/Pretty.hs
@@ -1,6 +1,10 @@
 module Pretty (prettyShow) where
 
+
 import qualified Data.Map as Map
+import qualified Data.Foldable as Foldable
+import qualified List
+
 import qualified CoreSyn
 import qualified Module
 import qualified HscTypes
@@ -8,12 +12,14 @@ import Text.PrettyPrint.HughesPJClass
 import Outputable ( showSDoc, ppr, Outputable, OutputableBndr)
 
 import qualified ForSyDe.Backend.Ppr
+import qualified ForSyDe.Backend.VHDL.Ppr
 import qualified ForSyDe.Backend.VHDL.AST as AST
 
 import HsValueMap
 import FlattenTypes
 import TranslatorTypes
 import VHDLTypes
+import CoreShow
 
 -- | A version of the default pPrintList method, which uses a custom function
 --   f instead of pPrint to print elements.
@@ -33,28 +39,50 @@ instance Pretty x => Pretty (HsValueMap x) where
 
 instance Pretty HsValueUse where
   pPrint Port            = char 'P'
-  pPrint (State n)       = char 'C' <> int n
+  pPrint (State n)       = char 'S' <> int n
   pPrint (HighOrder _ _) = text "Higher Order"
 
-instance Pretty id => Pretty (FlatFunction' id) where
-  pPrint (FlatFunction args res apps conds sigs) =
+instance Pretty FlatFunction where
+  pPrint (FlatFunction args res defs sigs) =
     (text "Args: ") $$ nest 10 (pPrint args)
     $+$ (text "Result: ") $$ nest 10 (pPrint res)
-    $+$ (text "Apps: ") $$ nest 10 (vcat (map pPrint apps))
-    $+$ (text "Conds: ") $$ nest 10 (pPrint conds)
-    $+$ text "Signals: " $$ nest 10 (printList ppsig sigs)
+    $+$ (text "Defs: ") $$ nest 10 (ppdefs defs)
+    $+$ text "Signals: " $$ nest 10 (ppsigs sigs)
     where
       ppsig (id, info) = pPrint id <> pPrint info
-
-instance Pretty id => Pretty (FApp id) where
+      ppdefs defs = vcat (map pPrint sorted)
+        where 
+          -- Roughly sort the entries (inaccurate for Fapps)
+          sorted = List.sortBy (\a b -> compare (sigDefDst a) (sigDefDst b)) defs
+          sigDefDst (FApp _ _ dst) = head $ Foldable.toList dst
+          sigDefDst (CondDef _ _ _ dst) = dst
+          sigDefDst (UncondDef _ dst) = dst
+      ppsigs sigs = vcat (map pPrint sorted)
+        where
+          sorted = List.sortBy (\a b -> compare (fst a) (fst b)) sigs
+
+
+instance Pretty SigDef where
   pPrint (FApp func args res) =
     pPrint func <> text " : " <> pPrint args <> text " -> " <> pPrint res
+  pPrint (CondDef cond true false res) = 
+    pPrint cond <> text " ? " <> pPrint true <> text " : " <> pPrint false <> text " -> " <> pPrint res
+  pPrint (UncondDef src dst) =
+    ppsrc src <> text " -> " <> pPrint dst
+    where
+      ppsrc (Left id) = pPrint id
+      ppsrc (Right expr) = pPrint expr
 
-instance Pretty id => Pretty (CondDef id) where
-  pPrint _ = text "TODO"
+instance Pretty SignalExpr where
+  pPrint (EqLit id lit) =
+    parens $ pPrint id <> text " = " <> text lit
+  pPrint (Literal lit) =
+    text lit
+  pPrint (Eq a b) =
+    parens $ pPrint a <> text " = " <> pPrint b
 
 instance Pretty SignalInfo where
-  pPrint (SignalInfo name use ty) =
+  pPrint (SignalInfo name use ty hints) =
     text ":" <> (pPrint use) <> (ppname name)
     where
       ppname Nothing = empty
@@ -92,16 +120,19 @@ instance Pretty FuncData where
       pparch (Just _) = text "VHDL architecture present"
 
 instance Pretty Entity where
-  pPrint (Entity id args res decl) =
+  pPrint (Entity id args res decl pkg) =
     text "Entity: " $$ nest 10 (pPrint id)
     $+$ text "Args: " $$ nest 10 (pPrint args)
     $+$ text "Result: " $$ nest 10 (pPrint res)
     $+$ ppdecl decl
+    $+$ pppkg pkg
     where
       ppdecl Nothing = text "VHDL entity not present"
       ppdecl (Just _) = text "VHDL entity present"
+      pppkg Nothing = text "VHDL package not present"
+      pppkg (Just _) = text "VHDL package present"
 
-instance (OutputableBndr b) => Pretty (CoreSyn.Bind b) where
+instance (OutputableBndr b, Show b) => Pretty (CoreSyn.Bind b) where
   pPrint (CoreSyn.NonRec b expr) =
     text "NonRec: " $$ nest 10 (prettyBind (b, expr))
   pPrint (CoreSyn.Rec binds) =
@@ -110,9 +141,9 @@ instance (OutputableBndr b) => Pretty (CoreSyn.Bind b) where
 instance Pretty AST.VHDLId where
   pPrint id = ForSyDe.Backend.Ppr.ppr id
 
-prettyBind :: (Outputable b, Outputable e) => (b, e) -> Doc
+prettyBind :: (Show b, Show e) => (b, e) -> Doc
 prettyBind (b, expr) =
   text b' <> text " = " <> text expr'
   where
-    b' = showSDoc $ ppr b
-    expr' = showSDoc $ ppr expr
+    b' = show b
+    expr' = show expr