Restructure a lot of VHDL generating code.

[matthijs/master-project/cλash.git] / Pretty.hs

diff --git a/Pretty.hs b/Pretty.hs
index 0cc2b59d98ab4f2ab36ae49aa5e812afdc4b3a60..7896372f2d27dd01603664e4602dac15901dce70 100644 (file)
--- a/Pretty.hs
+++ b/Pretty.hs
@@ -1,4 +1,4 @@
-module Pretty (prettyShow) where
+module Pretty (prettyShow, pprString) where
 
 
 import qualified Data.Map as Map
@@ -132,6 +132,9 @@ instance (OutputableBndr b, Show b) => Pretty (CoreSyn.Bind b) where
   pPrint (CoreSyn.Rec binds) =
     text "Rec: " $$ nest 10 (vcat $ map (prettyBind) binds)
 
+instance (OutputableBndr b, Show b) => Pretty (CoreSyn.Expr b) where
+  pPrint = text . show
+
 instance Pretty AST.VHDLId where
   pPrint id = ForSyDe.Backend.Ppr.ppr id
 
@@ -148,3 +151,7 @@ instance (Pretty k, Pretty v) => Pretty (Map.Map k v) where
     where
       ppentry (k, v) =
         pPrint k <> text " : " $$ nest 15 (pPrint v)
+
+-- Convenience method for turning an Outputable into a string
+pprString :: (Outputable x) => x -> String
+pprString = showSDoc . ppr