pPrint _ = text "TODO"
instance Pretty SignalInfo where
- pPrint (SignalInfo Nothing ty) = empty
- pPrint (SignalInfo (Just name) ty) = text ":" <> text name
+ pPrint (SignalInfo name use ty) =
+ text ":" <> (pPrint use) <> (ppname name)
+ where
+ ppname Nothing = empty
+ ppname (Just name) = text ":" <> text name
+
+instance Pretty SigUse where
+ pPrint SigPort = text "P"
+ pPrint SigInternal = text "I"
+ pPrint SigState = text "S"
+ pPrint SigSubState = text "s"
instance Pretty VHDLSession where
pPrint (VHDLSession mod nameCount funcs) =
$+$ text "NameCount: " $$ nest 15 (int nameCount)
$+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList funcs)))
where
- ppfunc (hsfunc, (FuncData flatfunc entity arch)) =
- pPrint hsfunc $+$ (text "Flattened: " $$ nest 15 (ppffunc flatfunc))
- $+$ (text "Entity") $$ nest 15 (ppent entity)
- $+$ pparch arch
+ ppfunc (hsfunc, fdata) =
+ pPrint hsfunc $+$ nest 5 (pPrint fdata)
+ modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
+
+instance Pretty FuncData where
+ pPrint (FuncData flatfunc entity arch) =
+ text "Flattened: " $$ nest 15 (ppffunc flatfunc)
+ $+$ text "Entity" $$ nest 15 (ppent entity)
+ $+$ pparch arch
+ where
ppffunc (Just f) = pPrint f
ppffunc Nothing = text "Nothing"
ppent (Just e) = pPrint e
ppent Nothing = text "Nothing"
pparch Nothing = text "VHDL architecture not present"
pparch (Just _) = text "VHDL architecture present"
- modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
instance Pretty Entity where
- pPrint (Entity args res decl) =
- text "Args: " $$ nest 10 (pPrint args)
+ pPrint (Entity id args res decl) =
+ text "Entity id: " $$ nest 10 (pPrint id)
+ $+$ text "Args: " $$ nest 10 (pPrint args)
$+$ text "Result: " $$ nest 10 (pPrint res)
$+$ ppdecl decl
where