Store a use for each signal in a flattened function.

[matthijs/master-project/cλash.git] / Pretty.hs

diff --git a/Pretty.hs b/Pretty.hs
index 21a3795ff6b71986f2d5bc897a2c844af16c8ae8..6f5f63dc71b46323fb582674992bd18e7c335d19 100644 (file)
--- a/Pretty.hs
+++ b/Pretty.hs
@@ -7,9 +7,13 @@ import qualified HscTypes
 import Text.PrettyPrint.HughesPJClass
 import Outputable ( showSDoc, ppr, Outputable, OutputableBndr)
 
+import qualified ForSyDe.Backend.Ppr
+import qualified ForSyDe.Backend.VHDL.AST as AST
+
 import HsValueMap
 import FlattenTypes
 import TranslatorTypes
+import VHDLTypes
 
 instance Pretty HsFunction where
   pPrint (HsFunction name args res) =
@@ -42,8 +46,18 @@ instance Pretty id => Pretty (FApp id) where
 instance Pretty id => Pretty (CondDef id) where
   pPrint _ = text "TODO"
 
-instance Pretty id => Pretty (Signal id) where
-  pPrint (Signal id) = pPrint id
+instance Pretty SignalInfo where
+  pPrint (SignalInfo name use ty) =
+    text ":" <> (pPrint use) <> (ppname name)
+    where
+      ppname Nothing = empty
+      ppname (Just name) = text ":" <> text name
+
+instance Pretty SigUse where
+  pPrint SigPort     = text "P"
+  pPrint SigInternal = text "I"
+  pPrint SigState    = text "S"
+  pPrint SigSubState = text "s"
 
 instance Pretty VHDLSession where
   pPrint (VHDLSession mod nameCount funcs) =
@@ -51,11 +65,32 @@ instance Pretty VHDLSession where
     $+$ text "NameCount: " $$ nest 15 (int nameCount)
     $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList funcs)))
     where
-      ppfunc (hsfunc, (FuncData flatfunc)) =
-        pPrint hsfunc $+$ (text "Flattened: " $$ nest 15 (ppffunc flatfunc))
+      ppfunc (hsfunc, fdata) =
+        pPrint hsfunc $+$ nest 5 (pPrint fdata)
+      modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
+
+instance Pretty FuncData where
+  pPrint (FuncData flatfunc entity arch) =
+    text "Flattened: " $$ nest 15 (ppffunc flatfunc)
+    $+$ text "Entity" $$ nest 15 (ppent entity)
+    $+$ pparch arch
+    where
       ppffunc (Just f) = pPrint f
       ppffunc Nothing  = text "Nothing"
-      modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
+      ppent (Just e)   = pPrint e
+      ppent Nothing    = text "Nothing"
+      pparch Nothing = text "VHDL architecture not present"
+      pparch (Just _) = text "VHDL architecture present"
+
+instance Pretty Entity where
+  pPrint (Entity id args res decl) =
+    text "Entity id: " $$ nest 10 (pPrint id)
+    $+$ text "Args: " $$ nest 10 (pPrint args)
+    $+$ text "Result: " $$ nest 10 (pPrint res)
+    $+$ ppdecl decl
+    where
+      ppdecl Nothing = text "VHDL entity not present"
+      ppdecl (Just _) = text "VHDL entity present"
 
 instance (OutputableBndr b) => Pretty (CoreSyn.Bind b) where
   pPrint (CoreSyn.NonRec b expr) =
@@ -63,6 +98,9 @@ instance (OutputableBndr b) => Pretty (CoreSyn.Bind b) where
   pPrint (CoreSyn.Rec binds) =
     text "Rec: " $$ nest 10 (vcat $ map (prettyBind) binds)
 
+instance Pretty AST.VHDLId where
+  pPrint id = ForSyDe.Backend.Ppr.ppr id
+
 prettyBind :: (Outputable b, Outputable e) => (b, e) -> Doc
 prettyBind (b, expr) =
   text b' <> text " = " <> text expr'