module Pretty (prettyShow) where
+
import qualified Data.Map as Map
+import qualified Data.Foldable as Foldable
+import qualified List
+
import qualified CoreSyn
import qualified Module
import qualified HscTypes
import Outputable ( showSDoc, ppr, Outputable, OutputableBndr)
import qualified ForSyDe.Backend.Ppr
+import qualified ForSyDe.Backend.VHDL.Ppr
import qualified ForSyDe.Backend.VHDL.AST as AST
import HsValueMap
import FlattenTypes
import TranslatorTypes
import VHDLTypes
+import CoreShow
+
+-- | A version of the default pPrintList method, which uses a custom function
+-- f instead of pPrint to print elements.
+printList :: (a -> Doc) -> [a] -> Doc
+printList f = brackets . fsep . punctuate comma . map f
instance Pretty HsFunction where
pPrint (HsFunction name args res) =
instance Pretty HsValueUse where
pPrint Port = char 'P'
- pPrint (State n) = char 'C' <> int n
+ pPrint (State n) = char 'S' <> int n
pPrint (HighOrder _ _) = text "Higher Order"
-instance Pretty id => Pretty (FlatFunction' id) where
- pPrint (FlatFunction args res apps conds sigs) =
+instance Pretty FlatFunction where
+ pPrint (FlatFunction args res defs sigs) =
(text "Args: ") $$ nest 10 (pPrint args)
$+$ (text "Result: ") $$ nest 10 (pPrint res)
- $+$ (text "Apps: ") $$ nest 10 (vcat (map pPrint apps))
- $+$ (text "Conds: ") $$ nest 10 (pPrint conds)
- $+$ text "Signals: " $$ nest 10 (pPrint sigs)
+ $+$ (text "Defs: ") $$ nest 10 (ppdefs defs)
+ $+$ text "Signals: " $$ nest 10 (ppsigs sigs)
+ where
+ ppsig (id, info) = pPrint id <> pPrint info
+ ppdefs defs = vcat (map pPrint sorted)
+ where
+ -- Roughly sort the entries (inaccurate for Fapps)
+ sorted = List.sortBy (\a b -> compare (sigDefDst a) (sigDefDst b)) defs
+ sigDefDst (FApp _ _ dst) = head $ Foldable.toList dst
+ sigDefDst (CondDef _ _ _ dst) = dst
+ sigDefDst (UncondDef _ dst) = dst
+ ppsigs sigs = vcat (map pPrint sorted)
+ where
+ sorted = List.sortBy (\a b -> compare (fst a) (fst b)) sigs
+
-instance Pretty id => Pretty (FApp id) where
+instance Pretty SigDef where
pPrint (FApp func args res) =
pPrint func <> text " : " <> pPrint args <> text " -> " <> pPrint res
+ pPrint (CondDef cond true false res) =
+ pPrint cond <> text " ? " <> pPrint true <> text " : " <> pPrint false <> text " -> " <> pPrint res
+ pPrint (UncondDef src dst) =
+ ppsrc src <> text " -> " <> pPrint dst
+ where
+ ppsrc (Left id) = pPrint id
+ ppsrc (Right expr) = pPrint expr
-instance Pretty id => Pretty (CondDef id) where
- pPrint _ = text "TODO"
+instance Pretty SignalExpr where
+ pPrint (EqLit id lit) =
+ parens $ pPrint id <> text " = " <> text lit
+ pPrint (Literal lit) =
+ text lit
+ pPrint (Eq a b) =
+ parens $ pPrint a <> text " = " <> pPrint b
instance Pretty SignalInfo where
- pPrint (SignalInfo Nothing ty) = empty
- pPrint (SignalInfo (Just name) ty) = text ":" <> text name
+ pPrint (SignalInfo name use ty hints) =
+ text ":" <> (pPrint use) <> (ppname name)
+ where
+ ppname Nothing = empty
+ ppname (Just name) = text ":" <> text name
+
+instance Pretty SigUse where
+ pPrint SigPortIn = text "PI"
+ pPrint SigPortOut = text "PO"
+ pPrint SigInternal = text "I"
+ pPrint (SigStateOld n) = text "SO:" <> int n
+ pPrint (SigStateNew n) = text "SN:" <> int n
+ pPrint SigSubState = text "s"
-instance Pretty VHDLSession where
- pPrint (VHDLSession mod nameCount funcs) =
+instance Pretty TranslatorSession where
+ pPrint (TranslatorSession mod nameCount flatfuncs) =
text "Module: " $$ nest 15 (text modname)
$+$ text "NameCount: " $$ nest 15 (int nameCount)
- $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList funcs)))
+ $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList flatfuncs)))
+ where
+ ppfunc (hsfunc, flatfunc) =
+ pPrint hsfunc $+$ nest 5 (pPrint flatfunc)
+ modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
+{-
+instance Pretty FuncData where
+ pPrint (FuncData flatfunc entity arch) =
+ text "Flattened: " $$ nest 15 (ppffunc flatfunc)
+ $+$ text "Entity" $$ nest 15 (ppent entity)
+ $+$ pparch arch
where
- ppfunc (hsfunc, (FuncData flatfunc entity arch)) =
- pPrint hsfunc $+$ (text "Flattened: " $$ nest 15 (ppffunc flatfunc))
- $+$ (text "Entity") $$ nest 15 (ppent entity)
- $+$ pparch arch
ppffunc (Just f) = pPrint f
ppffunc Nothing = text "Nothing"
ppent (Just e) = pPrint e
ppent Nothing = text "Nothing"
pparch Nothing = text "VHDL architecture not present"
pparch (Just _) = text "VHDL architecture present"
- modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
+-}
instance Pretty Entity where
- pPrint (Entity args res decl) =
- text "Args: " $$ nest 10 (pPrint args)
+ pPrint (Entity id args res) =
+ text "Entity: " $$ nest 10 (pPrint id)
+ $+$ text "Args: " $$ nest 10 (pPrint args)
$+$ text "Result: " $$ nest 10 (pPrint res)
- $+$ ppdecl decl
- where
- ppdecl Nothing = text "VHDL entity not present"
- ppdecl (Just _) = text "VHDL entity present"
-instance (OutputableBndr b) => Pretty (CoreSyn.Bind b) where
+instance (OutputableBndr b, Show b) => Pretty (CoreSyn.Bind b) where
pPrint (CoreSyn.NonRec b expr) =
text "NonRec: " $$ nest 10 (prettyBind (b, expr))
pPrint (CoreSyn.Rec binds) =
instance Pretty AST.VHDLId where
pPrint id = ForSyDe.Backend.Ppr.ppr id
-prettyBind :: (Outputable b, Outputable e) => (b, e) -> Doc
+prettyBind :: (Show b, Show e) => (b, e) -> Doc
prettyBind (b, expr) =
text b' <> text " = " <> text expr'
where
- b' = showSDoc $ ppr b
- expr' = showSDoc $ ppr expr
+ b' = show b
+ expr' = show expr
projects / matthijs / master-project / cλash.git / blobdiff