Redo the global (state) structure of the translator.

[matthijs/master-project/cλash.git] / Pretty.hs

diff --git a/Pretty.hs b/Pretty.hs
index 183125cc65761869c7221e8bb4b5c75c641e38f4..43e0e49bf7aa6c2dc3ce6822bf47306d57136175 100644 (file)
--- a/Pretty.hs
+++ b/Pretty.hs
@@ -1,6 +1,10 @@
 module Pretty (prettyShow) where
 
+
 import qualified Data.Map as Map
+import qualified Data.Foldable as Foldable
+import qualified List
+
 import qualified CoreSyn
 import qualified Module
 import qualified HscTypes
@@ -8,12 +12,14 @@ import Text.PrettyPrint.HughesPJClass
 import Outputable ( showSDoc, ppr, Outputable, OutputableBndr)
 
 import qualified ForSyDe.Backend.Ppr
+import qualified ForSyDe.Backend.VHDL.Ppr
 import qualified ForSyDe.Backend.VHDL.AST as AST
 
 import HsValueMap
 import FlattenTypes
 import TranslatorTypes
 import VHDLTypes
+import CoreShow
 
 -- | A version of the default pPrintList method, which uses a custom function
 --   f instead of pPrint to print elements.
@@ -33,26 +39,50 @@ instance Pretty x => Pretty (HsValueMap x) where
 
 instance Pretty HsValueUse where
   pPrint Port            = char 'P'
-  pPrint (State n)       = char 'C' <> int n
+  pPrint (State n)       = char 'S' <> int n
   pPrint (HighOrder _ _) = text "Higher Order"
 
 instance Pretty FlatFunction where
   pPrint (FlatFunction args res defs sigs) =
     (text "Args: ") $$ nest 10 (pPrint args)
     $+$ (text "Result: ") $$ nest 10 (pPrint res)
-    $+$ (text "Defs: ") $$ nest 10 (pPrint defs)
-    $+$ text "Signals: " $$ nest 10 (printList ppsig sigs)
+    $+$ (text "Defs: ") $$ nest 10 (ppdefs defs)
+    $+$ text "Signals: " $$ nest 10 (ppsigs sigs)
     where
       ppsig (id, info) = pPrint id <> pPrint info
+      ppdefs defs = vcat (map pPrint sorted)
+        where 
+          -- Roughly sort the entries (inaccurate for Fapps)
+          sorted = List.sortBy (\a b -> compare (sigDefDst a) (sigDefDst b)) defs
+          sigDefDst (FApp _ _ dst) = head $ Foldable.toList dst
+          sigDefDst (CondDef _ _ _ dst) = dst
+          sigDefDst (UncondDef _ dst) = dst
+      ppsigs sigs = vcat (map pPrint sorted)
+        where
+          sorted = List.sortBy (\a b -> compare (fst a) (fst b)) sigs
+
 
 instance Pretty SigDef where
   pPrint (FApp func args res) =
     pPrint func <> text " : " <> pPrint args <> text " -> " <> pPrint res
-  pPrint (CondDef _ _ _ _) = text "TODO"
-  pPrint (UncondDef src dst) = text "TODO"
+  pPrint (CondDef cond true false res) = 
+    pPrint cond <> text " ? " <> pPrint true <> text " : " <> pPrint false <> text " -> " <> pPrint res
+  pPrint (UncondDef src dst) =
+    ppsrc src <> text " -> " <> pPrint dst
+    where
+      ppsrc (Left id) = pPrint id
+      ppsrc (Right expr) = pPrint expr
+
+instance Pretty SignalExpr where
+  pPrint (EqLit id lit) =
+    parens $ pPrint id <> text " = " <> text lit
+  pPrint (Literal lit) =
+    text lit
+  pPrint (Eq a b) =
+    parens $ pPrint a <> text " = " <> pPrint b
 
 instance Pretty SignalInfo where
-  pPrint (SignalInfo name use ty) =
+  pPrint (SignalInfo name use ty hints) =
     text ":" <> (pPrint use) <> (ppname name)
     where
       ppname Nothing = empty
@@ -66,16 +96,16 @@ instance Pretty SigUse where
   pPrint (SigStateNew n) = text "SN:" <> int n
   pPrint SigSubState = text "s"
 
-instance Pretty VHDLSession where
-  pPrint (VHDLSession mod nameCount funcs) =
+instance Pretty TranslatorSession where
+  pPrint (TranslatorSession mod nameCount flatfuncs) =
     text "Module: " $$ nest 15 (text modname)
     $+$ text "NameCount: " $$ nest 15 (int nameCount)
-    $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList funcs)))
+    $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList flatfuncs)))
     where
-      ppfunc (hsfunc, fdata) =
-        pPrint hsfunc $+$ nest 5 (pPrint fdata)
+      ppfunc (hsfunc, flatfunc) =
+        pPrint hsfunc $+$ nest 5 (pPrint flatfunc)
       modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
-
+{-
 instance Pretty FuncData where
   pPrint (FuncData flatfunc entity arch) =
     text "Flattened: " $$ nest 15 (ppffunc flatfunc)
@@ -88,18 +118,15 @@ instance Pretty FuncData where
       ppent Nothing    = text "Nothing"
       pparch Nothing = text "VHDL architecture not present"
       pparch (Just _) = text "VHDL architecture present"
+-}
 
 instance Pretty Entity where
-  pPrint (Entity id args res decl) =
+  pPrint (Entity id args res) =
     text "Entity: " $$ nest 10 (pPrint id)
     $+$ text "Args: " $$ nest 10 (pPrint args)
     $+$ text "Result: " $$ nest 10 (pPrint res)
-    $+$ ppdecl decl
-    where
-      ppdecl Nothing = text "VHDL entity not present"
-      ppdecl (Just _) = text "VHDL entity present"
 
-instance (OutputableBndr b) => Pretty (CoreSyn.Bind b) where
+instance (OutputableBndr b, Show b) => Pretty (CoreSyn.Bind b) where
   pPrint (CoreSyn.NonRec b expr) =
     text "NonRec: " $$ nest 10 (prettyBind (b, expr))
   pPrint (CoreSyn.Rec binds) =
@@ -108,9 +135,9 @@ instance (OutputableBndr b) => Pretty (CoreSyn.Bind b) where
 instance Pretty AST.VHDLId where
   pPrint id = ForSyDe.Backend.Ppr.ppr id
 
-prettyBind :: (Outputable b, Outputable e) => (b, e) -> Doc
+prettyBind :: (Show b, Show e) => (b, e) -> Doc
 prettyBind (b, expr) =
   text b' <> text " = " <> text expr'
   where
-    b' = showSDoc $ ppr b
-    expr' = showSDoc $ ppr expr
+    b' = show b
+    expr' = show expr