Let mkCompInsSm look up the actual VHDL entity id.

[matthijs/master-project/cλash.git] / Pretty.hs

diff --git a/Pretty.hs b/Pretty.hs
index 98a3d33e9e7a15fe535caf9d23abb541cd5bd32c..2bf57f761541e3280bec0a32175c78a12d81b344 100644 (file)
--- a/Pretty.hs
+++ b/Pretty.hs
@@ -56,18 +56,27 @@ instance Pretty VHDLSession where
     $+$ text "NameCount: " $$ nest 15 (int nameCount)
     $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList funcs)))
     where
-      ppfunc (hsfunc, (FuncData flatfunc entity)) =
-        pPrint hsfunc $+$ (text "Flattened: " $$ nest 15 (ppffunc flatfunc))
-        $+$ (text "Entity") $$ nest 15 (ppent entity)
+      ppfunc (hsfunc, fdata) =
+        pPrint hsfunc $+$ nest 5 (pPrint fdata)
+      modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
+
+instance Pretty FuncData where
+  pPrint (FuncData flatfunc entity arch) =
+    text "Flattened: " $$ nest 15 (ppffunc flatfunc)
+    $+$ text "Entity" $$ nest 15 (ppent entity)
+    $+$ pparch arch
+    where
       ppffunc (Just f) = pPrint f
       ppffunc Nothing  = text "Nothing"
       ppent (Just e)   = pPrint e
       ppent Nothing    = text "Nothing"
-      modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
+      pparch Nothing = text "VHDL architecture not present"
+      pparch (Just _) = text "VHDL architecture present"
 
 instance Pretty Entity where
-  pPrint (Entity args res decl) =
-    text "Args: " $$ nest 10 (pPrint args)
+  pPrint (Entity id args res decl) =
+    text "Entity id: " $$ nest 10 (pPrint id)
+    $+$ text "Args: " $$ nest 10 (pPrint args)
     $+$ text "Result: " $$ nest 10 (pPrint res)
     $+$ ppdecl decl
     where