Generalize FApp and CondDef into SigDef and add UncondDef.

[matthijs/master-project/cλash.git] / Pretty.hs

diff --git a/Pretty.hs b/Pretty.hs
index bd4d9e598b3f798ca8b100d28e3bb5fce8004943..183125cc65761869c7221e8bb4b5c75c641e38f4 100644 (file)
--- a/Pretty.hs
+++ b/Pretty.hs
@@ -7,9 +7,18 @@ import qualified HscTypes
 import Text.PrettyPrint.HughesPJClass
 import Outputable ( showSDoc, ppr, Outputable, OutputableBndr)
 
+import qualified ForSyDe.Backend.Ppr
+import qualified ForSyDe.Backend.VHDL.AST as AST
+
 import HsValueMap
 import FlattenTypes
 import TranslatorTypes
+import VHDLTypes
+
+-- | A version of the default pPrintList method, which uses a custom function
+--   f instead of pPrint to print elements.
+printList :: (a -> Doc) -> [a] -> Doc
+printList f = brackets . fsep . punctuate comma . map f
 
 instance Pretty HsFunction where
   pPrint (HsFunction name args res) =
@@ -27,25 +36,35 @@ instance Pretty HsValueUse where
   pPrint (State n)       = char 'C' <> int n
   pPrint (HighOrder _ _) = text "Higher Order"
 
-instance Pretty id => Pretty (FlatFunction' id) where
-  pPrint (FlatFunction args res apps conds) =
+instance Pretty FlatFunction where
+  pPrint (FlatFunction args res defs sigs) =
     (text "Args: ") $$ nest 10 (pPrint args)
     $+$ (text "Result: ") $$ nest 10 (pPrint res)
-    $+$ (text "Apps: ") $$ nest 10 (vcat (map pPrint apps))
-    $+$ (text "Conds: ") $$ nest 10 (pPrint conds)
+    $+$ (text "Defs: ") $$ nest 10 (pPrint defs)
+    $+$ text "Signals: " $$ nest 10 (printList ppsig sigs)
+    where
+      ppsig (id, info) = pPrint id <> pPrint info
 
-instance Pretty id => Pretty (FApp id) where
+instance Pretty SigDef where
   pPrint (FApp func args res) =
     pPrint func <> text " : " <> pPrint args <> text " -> " <> pPrint res
+  pPrint (CondDef _ _ _ _) = text "TODO"
+  pPrint (UncondDef src dst) = text "TODO"
 
-instance Pretty id => Pretty (SignalDef id) where
-  pPrint (SignalDef id) = pPrint id
-
-instance Pretty id => Pretty (SignalUse id) where
-  pPrint (SignalUse id) = pPrint id
+instance Pretty SignalInfo where
+  pPrint (SignalInfo name use ty) =
+    text ":" <> (pPrint use) <> (ppname name)
+    where
+      ppname Nothing = empty
+      ppname (Just name) = text ":" <> text name
 
-instance Pretty id => Pretty (CondDef id) where
-  pPrint _ = text "TODO"
+instance Pretty SigUse where
+  pPrint SigPortIn   = text "PI"
+  pPrint SigPortOut  = text "PO"
+  pPrint SigInternal = text "I"
+  pPrint (SigStateOld n) = text "SO:" <> int n
+  pPrint (SigStateNew n) = text "SN:" <> int n
+  pPrint SigSubState = text "s"
 
 instance Pretty VHDLSession where
   pPrint (VHDLSession mod nameCount funcs) =
@@ -53,16 +72,42 @@ instance Pretty VHDLSession where
     $+$ text "NameCount: " $$ nest 15 (int nameCount)
     $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList funcs)))
     where
-      ppfunc (hsfunc, (FuncData flatfunc)) =
-        pPrint hsfunc $+$ (text "Flattened: " $$ nest 15 (pPrint flatfunc))
+      ppfunc (hsfunc, fdata) =
+        pPrint hsfunc $+$ nest 5 (pPrint fdata)
       modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
 
+instance Pretty FuncData where
+  pPrint (FuncData flatfunc entity arch) =
+    text "Flattened: " $$ nest 15 (ppffunc flatfunc)
+    $+$ text "Entity" $$ nest 15 (ppent entity)
+    $+$ pparch arch
+    where
+      ppffunc (Just f) = pPrint f
+      ppffunc Nothing  = text "Nothing"
+      ppent (Just e)   = pPrint e
+      ppent Nothing    = text "Nothing"
+      pparch Nothing = text "VHDL architecture not present"
+      pparch (Just _) = text "VHDL architecture present"
+
+instance Pretty Entity where
+  pPrint (Entity id args res decl) =
+    text "Entity: " $$ nest 10 (pPrint id)
+    $+$ text "Args: " $$ nest 10 (pPrint args)
+    $+$ text "Result: " $$ nest 10 (pPrint res)
+    $+$ ppdecl decl
+    where
+      ppdecl Nothing = text "VHDL entity not present"
+      ppdecl (Just _) = text "VHDL entity present"
+
 instance (OutputableBndr b) => Pretty (CoreSyn.Bind b) where
   pPrint (CoreSyn.NonRec b expr) =
     text "NonRec: " $$ nest 10 (prettyBind (b, expr))
   pPrint (CoreSyn.Rec binds) =
     text "Rec: " $$ nest 10 (vcat $ map (prettyBind) binds)
 
+instance Pretty AST.VHDLId where
+  pPrint id = ForSyDe.Backend.Ppr.ppr id
+
 prettyBind :: (Outputable b, Outputable e) => (b, e) -> Doc
 prettyBind (b, expr) =
   text b' <> text " = " <> text expr'